Today 19 /10/2017 to gather 20/10/2017
Hardware
Components
Components
List of 4000 series family in integrated circuits
List of the CMOS 4000 series
- 4000 series - Family specification (IC04) - The family specification applies to each of the following circuits.
Manufacturers
Non-exhaustive list of manufacturers which make or have made these kind of circuits.- Fairchild Semiconductor ]
- Hitachi
- Intersil [2]
- National Semiconductor
- NXP Semiconductors [3]
- ON Semiconductor [4]
- ST Microelectronics [5]
- Texas Instruments [6]
- Toshiba Semiconductor [7]
- VEB Kombinat Mikroelektronik (former East-German manufacturer in the 1980s)
Categories
- Adders
- Analog Switches
- Buffers
- Counters
- Flip-Flops (D, JK types)
- Latches
- LCD Drivers
- Logic Gates (NAND, NOR, XOR, NOT, etc.)
- Multiplexers (Multiplexer(s), Demultiplexer(s), Encoder(s), Decoder(s))
- Registers, Shift Registers
- Timers
- Translators (Logic Level Translators)
- 7-Segment Decoders
The 4000 series is a family of integrated circuits (ICs) first introduced in 1968. Almost all IC manufacturers active during this initial era fabricated models for this series. It is still in use today.
The 4000 series was introduced as the CD4000 COS/MOS series in 1968 by RCA as a lower power and more versatile alternative to the 7400 series of transistor-transistor logic (TTL) chips. The logic functions were implemented with the newly introduced Complementary Metal–Oxide–Semiconductor (CMOS) technology. While initially marketed with "COS/MOS" labeling by RCA (which stood for Complementary Symmetry Metal-Oxide Semiconductor), the shorter CMOS terminology emerged as the industry preference to refer to the technology.[1] The first chips in the series were designed by a group led by Albert Medwin.[2]Wide adoption was initially hindered by the comparatively slower speeds of the designs compared to TTL based designs. Speed limitations were eventually overcome with newer fabrication methods, leaving the older TTL chips to be phased out. The series was extended in the late 1970s and 1980s with new models that were given 45xx and 45xxx designations, but are usually still regarded by engineers as part of the 4000 series. In the 1990s, some manufacturers (e.g. Texas Instruments) ported the 4000 series to newer HCMOS based designs to provide greater speeds.
Design considerations
The CD4007 on a breadboard
Common 4000 series chips
- 4001 - Quad 2-input NOR gate
- 4008 - 4-bit full adder
- 4011 - Quad 2-input NAND gate
- 4013 - Dual D Type Flip Flop
- 4017 - Decade counter / walking ring counter
- 4026 - 7-segment LED counter
- 4049 - Hex inverting buffer
- 4050 - Hex non-inverting buffer
- 4051 - 8-channel analog multiplexer / demultiplexer
- 4071 - Quad 2-input OR gate
- 4081 - Quad 2-input AND gate
Q . III 7400 series CMOS vs 4000 series logic IC
Q . II 74 Series Logic ICs There are several families of logic ICs numbered from 74xx00 onwards with letters (xx) in the middle of the number to indicate the type of circuitry, eg 74LS00 and 74HC00. The original family (now obsolete) had no letters, eg 7400. This page covers a selection of the many ICs in the 74 series, concentrating on the most useful gates, counters, decoders and display drivers. For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary. For simplicity the family letters after the 74 are omitted in the diagrams below because the pin connections apply to all ICs with the same number. For example 7400 NAND gates are available as 74HC00, 74HCT00 and 74LS00. If you are using another reference please be aware that there is some variation in the terms used to describe pin functions, for example reset is also called clear. Some inputs are 'active low' which means they perform their function when low. 74 series families
The 74LS (Low-power Schottky) family (like the original) uses TTL (Transistor-Transistor Logic) circuitry which is fast but requires more power than later families. The 74 series is often still called the 'TTL series' even though the latest ICs do not use TTL!
The 74HC family has High-speed CMOS circuitry, combining the speed of TTL with the very low power consumption of the 4000 series. They are CMOS ICs with the same pin arrangements as the older 74LS family. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible, use 74HCT instead. The 74HCT family is a special version of 74HC with 74LS TTL-compatible inputs so 74HCT can be safely mixed with 74LS in the same system. In fact 74HCT can be used as low-power direct replacements for the older 74LS ICs in most circuits. The minor disadvantage of 74HCT is a lower immunity to noise, but this is unlikely to be a problem in most situations. For most new projects the 74HC family is the best choice. The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.  Open Collector Outputs
Some 74 series ICs have open collector outputs, this means they can sink current but they cannot source current. They behave like an NPN transistor switch.
The diagram shows how an open collector output can be connected to sink current from a supply which has a higher voltage than the logic IC supply. The maximum load supply is 15V for most open collector ICs. Open collector outputs can be safely connected together to switch on a load when any one of them is low; unlike normal outputs which must be combined using diodes.  74HC and 74HCT family characteristics
74LS family TTL characteristics
Quad 2-input gates
 7402 quad 2-input NORThe 7402 IC is shown separately because it has an unusual gate layout. Triple 3-input gates
 Dual 4-input gates
 7430 8-input NAND gateNC = No Connection (unused pin). Hex NOT gates
7490 decade (0-9) ripple counter
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NC = No Connection (unused pin).
For normal use connect QA to clockB and connect external clock signal to clockA.
* reset and preset are both active-low 
* preset is active-low
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM10 | Op-amp with an adjustable voltage reference [5] | ||
| LM101 LM201 LM301 | μA709[1] | General purpose op-amp with external compensation[6] | |
| LM107 LM207 LM307 | μA709 | Yes | General purpose op-amp[7] |
| LM108 LM208 LM308 | Yes | Precision op-amp[8] | |
| LM112 LM212 LM312 | Yes | Micropower op-amp with external compensation[9] | |
| LM118 LM218 LM318 | Precision, fast general purpose op-amp with external compensation[10] | ||
| LM321 | Low power op-amp[11] | ||
| LM124 LM224 LM324 LM2902 | Quadruple wide supply range op-amps[12] | ||
| LM146 LM346 | only LM146 | Programmable quadruple op-amps[13][14] | |
| LM148 LM248 LM348 | General purpose quadruple op-amps[15] | ||
| LM158 LM258 LM358 LM2904 | Low power, wide supply range dual op-amps[16] | ||
| LM392 | Low power dual op-amps and comparator[17] | ||
| LM432 | LM358, LMV431 | Dual op-amps with fixed 2.5 V reference[18] | |
| LM611 | Op-amp with an adjustable voltage reference[19] | ||
| LM614 | Quadruple op-amps with an adjustable voltage reference[20] | ||
| LM675 | Power op-amp with a maximal current output of 3 amperes[21] | ||
| LM709 | Yes | General purpose op-amp[22] | |
| LM741 | LM709 | General purpose op-amp[23] | |
| LM748 | General purpose op-amp with external compensation[24] | ||
| LM833 | Dual high speed audio operational amplifiers[25] | ||
| LM837 | Low noise quadruple op-amps [26] |
Differential comparators
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM306 | High speed differential comparator with strobes[27] | ||
| LM111 LM211 LM311 | LM106 LM710 | High speed differential comparator with strobes[28] | |
| LM119 LM219 LM319 | LM711(?) | High speed dual comparators[29] | |
| LM139 LM239 LM339 LM2901 | Quadruple wide supply range comparators[30] | ||
| LM160 LM360 | μA760 | High speed comparator with complementary TTL outputs[31] | |
| LM161 LM361 | only LM161 | High speed comparator with strobed complementary TTL outputs[32][33] | |
| LM193 LM293 LM393 LM2903 | Dual wide supply range comparators[34] | ||
| LM397 | General purpose comparator with an input common mode[35] | ||
| LM613 | Dual op-amps, dual comparators and adjustable reference[36] |
Current-mode amplifiers
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM359 | Dual, high speed, programmable current mode amplifiers[37] |
Instrumentation amplifiers
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM363 | Yes | Precision instrumentation amplifier[38] |
Audio amplifiers
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM380 | 2.5 W audio power amplifier (fixed 34 dB gain)[39] | ||
| LM384 | 5 W audio power amplifier (fixed 34 dB gain)[40] | ||
| LM1875 | 20 W audio power amplifier (up to 90 dB gain)[41] | ||
| LM1876 | Dual 20 W audio power amplifier with Mute and Standby Modes (up to 90 dB gain)[42] | ||
| LM386 | Low voltage audio power amplifier[43] | ||
| LM3875 | High-performance 56 W audio power amplifier[44] | ||
| LM3886 | High-performance 68 W audio power amplifier[45] |
Precision reference
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM113 LM313 | only LM313 | Temperature compensated Zener reference diode, 1.22 V breakdown voltage[46][47] | |
| LM329 | Temperature compensated Zener reference diode, 6.9 V breakdown voltage[48] | ||
| LM136 LM236 LM336 | 2.5 V or 5 V Zener reference diode with temperature coefficient trimmer[49] | ||
| LM368 | Yes | 2.5 V precision voltage reference[50] | |
| LM169 LM369 | LM199 | Yes | 2.5 V temperature compensated precision voltage reference[51] |
| LM185 LM285 LM385 | Fixed (1.2 V, 2.5 V) or adjustable micropower voltage reference[52] | ||
| LM199 LM299 LM399 | Yes (by TI, still produced by LT) | Fixed (6.95 V) voltage reference[53] | |
| LM431 | Adjustable precision Zener shunt regulator (2.5 V-36 V)[54] |
Voltage regulators
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM105 LM305 | LM100 | Adjustable positive voltage regulator (4.5 V-40 V)[55] | |
| LM109 LM309 | 5-volt regulator (up to 1 A)[56] | ||
| LM117 LM317 | Adjustable 1.5 A positive voltage regulator (1.25 V-37 V)[57] | ||
| LM120 LM320 | Fixed 1.5 A negative voltage regulator (-5 V, -12 V, -15 V)[58] | ||
| LM123 LM323 | Fixed 3 A, 5-volt positive voltage regulator[59] | ||
| LM325 | Yes | Dual ±15-volt voltage regulator[60] | |
| LM330 | 5-volt positive voltage regulator, 0.6 V input-output difference[61] | ||
| LM333 | Yes | Adjustable 3 A negative voltage regulator (-1.2 V to -32 V)[62] | |
| LM237 LM337 | Adjustable 1.5 A negative voltage regulator (-1.2 V to -37 V)[63] | ||
| LM138 LM338 | Adjustable 5 A voltage regulator (1.2 V-32 V)[64] | ||
| LM140 LM340 | LM78xx | 1 A positive voltage regulator (5 V, 12 V, 15 V), can be adjustable[65][66] | |
| LM341 LM78Mxx | 0.5 A protected positive voltage regulators (5 V, 12 V, 15 V)[67] | ||
| LM145 LM345 | Yes | Fixed 3 A, -5-volt negative voltage regulator[68] | |
| LM150 LM350 | only LM150 | Adjustable 3 A, positive voltage regulator (1.2 V-33 V)[69][70] | |
| LM78xx | Fixed 1 A positive voltage regulators (5 V-24 V)[71] | ||
| LM79xx | Fixed 1.5 A negative voltage regulators (-5 V, -12 V, -15 V)[72] | ||
| LM2576 | Fixed and adjustable 3 A buck/buck-boost switching regulators [73] |
Voltage-to-frequency converters
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM231 LM331 | Precision voltage-to-frequency converter (1 Hz-100 kHz)[74] |
Current sources
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM134 LM234 LM334 | Adjustable current source (1 μA-10 mA)[75] |
Temperature sensors and thermostats
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM19 | Temperature sensor, 2.5 °C accuracy[76] | ||
| LM20 | Temperature sensor, 1.5 °C accuracy[77] | ||
| LM26 | Factory preset thermostat, 3 °C accuracy[78] | ||
| LM27 | Factory preset thermostat (120 °C-150 °C), 3 °C accuracy[79] | ||
| LM34 | Precision Fahrenheit temperature sensor, 0.5 °F accuracy[80] | ||
| LM35 | Precision Celsius temperature sensor, 0.25 °C accuracy[81] | ||
| LM45 | Precision Celsius temperature sensor, 2 °C accuracy[82] | ||
| LM50 | Single supply Celsius temperature sensor, 2 °C accuracy[83] | ||
| LM56 | Dual output resistor programmable thermostat with analog temperature sensor[84] | ||
| LM60 LM61 LM62 | Single supply Celsius temperature sensors (The difference between the components is the voltage scale)[85] | ||
| LM75A | Digital temperature sensor and programmable thermostat.[86] | ||
| LM135 LM235 LM335 | Precision Zener temperature sensor, 1 °C accuracy[87] |
| Part number | Predecessor | Obsolete? | Description |
|---|---|---|---|
| LM3914 | Dot / bar graph display driver | ||
| LM13700 | Operational transconductance amplifier (OTA) |
Notes
- Suffixes that denote specific versions of the part (e.g. LM305 vs. LM305A) are not shown in this list.
- The first digit of each part denote different temperature ranges. Mostly, LM1xx indicates military-grade temperature range of -55 °C to +125 °C, LM2xx indicates industrial-grade temperature range of -25 °C to +85 °C and LM3xx indicates commercial temperature range of 0 °C to 70 °C.
- Some of the obsolete parts are continued to be manufactured by different companies other than the original manufacturer, e.g. Fairchild Semiconductor
Q . IIIII 74HCT Series Chips
74HCT Series Chips
The 74HCT family of logic devices are high speed, low power devices that use CMOS circuitry. The devices are pin compatible with many existing devices such as the 74TTL, 74STTL, 4000 series and the 74LS family.
- 4.5V to 5.5V operation
- Very high impedance inputs
- Can sink and source approx. 20mA
- Large fan-out capability
Q . IIIIII Understanding Digital Logic ICs
One of the most important events in the history of digital electronics was the development of the new IC technology known as CMOS in 1969. CMOS (Complementary-symmetry MOSFET) digital IC elements have major advantages over TTL types. They are simple and inexpensive, consume near-zero quiescent current, have a very high input impedance, can operate over a wide range of supply voltages, have excellent noise immunity, and are very easy to use.
In 1972, practical CMOS arrived on the commercial scene in the form of a brand-new medium-speed family of digital ICs known as the ’4000’-series. This new family was not as fast as the TTL technology then in use in the rival ‘74’-series of digital ICs, but in the mid 1980s, a new high-speed type of CMOS was developed and introduced as a new member of the 74 family of devices. The advantages of this new ‘fast’ CMOS were so great that in 1994, it overtook TTL in popularity within the 74-series, finally making CMOS the most popular of all modern digital IC technologies.
This final episode explains the operating principles of these 4000- and 74-series CMOS devices, and describes CMOS basic usage rules.
CMOS Basics
The most basic element in any digital IC family is the digital inverter. Figure 1 (repeated from Part 1 of this four-part series) shows a basic CMOS inverter.
FIGURE 1. Circuit and Truth Table of a basic CMOS inverter.
It is a ‘totem-pole’ type of amplifier and consists of a complementary pair of enhancement-mode MOSFETs wired in series between the two supply lines, with p-channel MOSFET Q1 at the top and n-channel MOSFET Q2 below and with the MOSFET gates (which have a near-infinite DC input impedance) tied together at the input terminal and the output taken from the junction of the two devices. The pair can be powered from any supply in the 3V to 15V range. The basic digital action of the n-channel device is such that its drain-to-source path acts like an open-circuit switch when the input is at logic-0, or as a closed switch in series with a 400Ω resistor when the input is at logic-1. The p-channel MOSFET has the inverse of these characteristics, and acts like a closed switch plus a 400Ω resistance with a logic-0 input, and an open switch with a logic-1 input. The basic action of the CMOS inverter can be understood with the help of Figure 2.
FIGURE 2. Equivalent circuit of the CMOS digital inverter with (a) logic-0 and (b) logic-1 inputs.
Figure 2(a) shows the digital equivalent of the CMOS inverter circuit with a logic-0 input. Under this condition, Q1 (the p-channel MOSFET) acts like a closed switch in series with 400Ω, and Q2 acts like an open switch. The circuit thus draws zero quiescent current but can ‘source’ fairly large drive currents into an external output-to-ground load via the 400Ω output resistance (R1) of the inverter. Figure 2(b) shows the inverter’s equivalent circuit with a logic-1 input. In this case, Q1 acts like an open switch, but Q2 (the n-channel MOSFET) acts like a closed switch in series with 400Ω; the inverter thus draws zero quiescent current under this condition, but can ‘sink’ fairly large currents from an external supply-to-output load via its internal 400Ω output resistance (R2).
Thus, the basic CMOS digital inverter can be used with any supply in the 3V to 15V range, has a near-infinite input impedance, draws near-zero (typically 0.01 µA) supply current with a logic-0 or logic-1 input, can source or sink substantial output currents, and has an output impedance of about 400W. Note that, unlike the TTL inverter, its output can swing all the way from zero to the full positive supply rail value, since no potentials are lost via saturation or forward-biased junction voltages, etc. Typically, a basic (mid 1970s style) CMOS stage has a propagation delay ranging from 12 ns when using a 12V supply, to 60 nS at 3V, etc.
The ‘4000A’-Series of ICs
The initial 1972 range of digital ICs was known as the ‘4000A’ series; it used the basic type of CMOS inverter shown in Figure 1, but incorporated extensive diode-resistor ‘clamping’ networks to protect its MOSFETs against damage from static charges, etc. Thus, a complete A-series inverter stage took the basic form shown in Figure 3.
FIGURE 3. Basic 4000A-series inverter stage, with internal input and output protection networks.
Commercial testing of the early A-series range of CMOS devices quickly revealed a number of design problems. Their on-off resistance values were, for example, very sensitive to gamma radiation effects, thus limiting their value in outer-space projects, and they gave uneven ‘high’ and ‘low’ output impedances and propagation delays, etc. (i .e., they had poor output symmetry). But the most important problem was that their output switching levels were overly sensitive to the magnitudes of their input switching signals; the root cause of this problem can be understood with the aid of Figure 4, which shows the linear characteristics of the CMOS inverter’s two MOSFETs when they are operated from a 15 volt supply.
FIGURE 4. Typical gate-volts/drain-current characteristics of p- and n-channel MOSFETs operating from a 15V supply.
Note in Figure 4 that each MOSFET acts like a voltage-controlled resistance. The n-channel device has a near-infine drain-to-source resistance at zero input voltage: the resistance remains high until the input rises to a ‘threshold’ value of about 1.5 to 2.5 volts, but then decreases as the input voltage is increased, eventually falling to about 400Ω when the input equals the supply line voltage. The p-channel MOSFET has the reverse of these characteristics. Thus, when the two MOSFETs are wired in series and used as a 15 volt basic CMOS inverter, they produce the typical drain-current transfer graph shown in Figure 5, and the voltage transfer graph of Figure 6; these graphs can be explained as follows.
FIGURE 5. Typical drain-current transfer characteristics of the simple CMOS inverter.
FIGURE 6. Typical voltage transfer characteristics of the simple CMOS inverter.
Suppose in Figures 5 and 6 that the CMOS inverter’s input voltage is slowly increased upwards from zero. The inverter current is near zero until the input exceeds the n-channel MOSFET’s threshold voltage, at which point its resistance starts to fall and that of the p-channel MOSFET starts to increase. Under this condition, the inverter current is dictated by the larger of the two resistances; when the input is far less than half-supply volts, the n-channel MOSFET resistance is far greater than that of the p-channel device, so the output is high (at logic-1).
When the input is at a transition value somewhere between 30 and 70 percent of the supply voltage, the two MOSFETs have similar resistance values and the inverter acts as a linear amplifier with a voltage gain of about 30 dB and draws several milliamps of supply current. Under this condition, small changes of input voltage cause large changes of output voltage. When the input is further increased — well above half-supply volts — the resistance of the n-channel MOSFET falls below that of the p-channel device, and the output goes low (to logic-0). Finally, when the input rises above the threshold value of the p-channel MOSFET, it acts like an open switch, and the inverter current again falls to near zero.
Thus, the A-series type of inverter gives an output that switches fully between the supply rail values only if its input voltage swings well above and below its two internal threshold voltage values. Note (from Figure 5) that the CMOS draws a brief pulse of supply current each time it goes through a switching transition; the more often CMOS changes state in a given time, the greater are the number of current pulses that it takes from the supply and the greater is its mean current consumption. Thus, CMOS current consumption is directly proportional to switching frequency.
The ‘4000B’-Series of ICs
The defects of the 4000A-series were so severe that an improved CMOS series, known as the ‘4000B’ or buffered series, was introduced around 1975, and the old 4000A-series was slowly phased out of production. The major feature of this new series is that each of its ‘inverters’ consists of three basic inverters wired in series, as shown in Figure 7, so that each ‘buffered’ inverter has a typical linear voltage gain of 70 to 90 dB and has the typical voltage transfer graph of Figure 8, in which any input below VDD/3 is recognized as a logic-0 input and any input above 2VDD/3 is recognized as a logic-1 input.
FIGURE 7. A B-series CMOS inverter can be made by wiring three A-series types in series.
FIGURE 8. Voltage transfer graph of the Figure 7 B-series inverter.
Other changes in the new series include greatly improved output-drive symmetry and immunity to gamma-radiation effects, new and better input and output protection networks (see Figure 9), and improved voltage ratings (usually to 15V maximum, but to 18V maximum in some manufacturer’s versions, compared to 12V maximum in the original A-series).
FIGURE 9. Basic 4000B-series inverter with typical input and output protection networks.
One disadvantage of the B-series is that its propagation delays are larger than those of the old A-series. To counter this problem, a few new-generation devices are produced in an ‘unbuffered’ format (denoted by a ‘UB’ suffix), but incorporate all the other improvements of the B-series.
Typically, UB inverters have an AC gain of 23 dB at 10 volts, and are useful in several analog applications. Note that the bandwidth and propagation delays of a CMOS device vary with supply voltage and with capacitive output loading. Figure 10 lists the typical propagation delays of both UB and B-series inverters when used with supply values of 5V, 10V, and 15V when driving a 50 pF load.
FIGURE 10. Typical propagation delays of 4000B-series inverters when driving a 50 pF load.
The ‘4500B’-Series of ICs
The 4000B-series range of ICs consists mainly of fairly simple SSI or MSI devices such as logic gates and simple counters, etc. In the late 1970s and early 1980s, a number of more complex MSI and LSI B-type CMOS ICs such as encoders, decoders, and presettable counters (etc.), were introduced. These advanced devices carry ‘45XX’ or ‘47XX’ numbers, and are generally known as the 4500-series of CMOS ICs.‘Fast’ CMOS ICs
In the early 1980s, engineers strove to design a really fast type of CMOS that could outclass LS TTL when operated from a five-volt supply and could thus become the dominant technology within the 74 series of ICs. Normal CMOS is based on MOSFET (Metal-Oxide Silicon FET) technology, and this is simply a variation of IGFET (Insulated-Gate FET) technology. Specifically, a MOSFET device is an IGFET device that uses metal-oxode gate insulation, and the first big step in developing ‘fast’ CMOS was to use silicon-oxide rather than metal-oxide gate insulation in the basic IGFETs.This simple measure resulted in a dramatic reduction in the IGFET’s internal input capacitance and an equally dramatic increase in operating speed. The next step was to apply these new IGFETs to the basic CMOS configuration. When this was done and significant changes were made in the element’s geometry, the resulting device acted like normal CMOS but was as fast as LS TTL when operated from a five-volt supply and (unlike some other versions of CMOS) had excellent output drive capability. Strictly, this new device should have been given a special name such as CSOS (Complementary Silicon-Oxide Silicon FET), but instead was simply christened ‘fast’ CMOS.
Fast CMOS has many similarities with conventional 4000B-series CMOS. It is available in both buffered (triple-inverter) and unbuffered (single inverter) basic versions, and has all inputs and outputs protected via internal diode-resistor networks. It can (in most cases) use any supply in the 2V to 6V range, and when first introduced, was intended to replace many existing devices in the 74 series of ICs. Since then, however, it has also been used to make fast versions of many popular devices within the 4000B and 4500B series of ICs.
CMOS 74-Series Sub-Families
When the 74-series of IC first appeared in 1972, it was based entirely on TTL technology, which inherently consumes a fairly high quiescent current. In the late 1970s, a slightly modified version of standard CMOS (optimized for 5V operation) was introduced as a new ‘C’ sub-family within the 74-series range of devices, and offered the advantage of near-zero quiescent current consumption. This C sub-family was too slow and had too weak an output-drive capability to obtain great popularity, but in later years, the fast type of CMOS was developed specifically for use in the 74-series, as already described, and so far a total of five CMOS sub-families have been introduced in the 74-series, as follows:- Standard (C) CMOS (now obsolete). This was virtually normal MOSFET-type CMOS in a 74-series format. Typically, a single 74C00 two-input NAND gate consumed about 15 mW at 10 MHz, and had a propagation delay of 60 nS at 5V.
- High-speed (HC) CMOS. Introduced in the early 1980s, this is the basic fast silicon-oxide version of CMOS, and gives speed performances similar to LS TTL, but with CMOS levels of power consumption. HC 74-series devices using this technology have CMOS-compatible inputs. Typically, a single 74HC00 two-input NAND gate consumes less than 1 µA of quiescent current, and has a propagation delay of 8 nS at 5V.
- High-speed (HCT) CMOS. These are fast HC-type devices, but have TTL-compatible inputs and are meant to be driven directly from TTL outputs. Typically, a 74HCT00 two-input NAND gate consumes less than 1 µA of quiescent current and has a propagation delay of 18 nS.
- Advanced high-speed (AC) CMOS. In the late 1980s, further advances in high-speed CMOS design and fabrication techniques yielded even better speed performances. AC 74-series devices using this technology have CMOS-compatible inputs. Typically, a 74AC00 two-input NAND gate has a propagation delay of 5 nS.
- Advanced high-speed (ACT) CMOS. These are AC-type devices, but have TTL-compatible inputs and are meant to be driven from TTL outputs. Typically, a 74ACT00 two-input NAND gate has a propagation delay of 7 nS.
Basic CMOS Circuit Variations
There are three important variations of the basic CMOS circuit that are often used in ICs in the medium-speed 4000B-series and fast 74-series ranges of devices. The first of these is the ‘open drain’ configuration, which is used in some inverters and buffers, etc. Figure 11 shows a typical open-drain inverter, which is configured like a normal high-gain three-stage CMOS inverter except that the final stage consists of a single n-channel enhancement-mode IGFET (Q1) that has its drain connected directly to the circuit’s output terminal.
FIGURE 11. Basic CMOS inverter with open-drain output.
The circuit’s action is such that Q1 is cut off when the input is at logic-0, and is driven on when the input is at logic-1. The circuit can be used to directly drive an external load that is connected between ‘OUT’ and the +ve supply rail, in which case the load activates when a logic-1 input is applied.
The second variation concerns the use of a ‘three-state’ type of output that in normal use gives a conventional logic-0 or logic-1 low-impedance output, but can also be set to a third state in which the output is effectively open-circuit. This facility is useful in allowing several outputs or inputs to be wired to a common bus and to communicate along that bus by ENABLING only one output and one input device at a time.
Figure 12 shows the typical circuit of a non-inverting buffer of this type, together with its truth table.
FIGURE 12. Basic circuit of a three-state CMOS non-inverting buffer.
Thus, when the DISABLE INPUT control is at logic-0, the circuit gives normal ‘buffer’ operation; under this condition, Q1 is driven OFF and Q2 is driven ON when IN is at logic-0, thus driving OUT to logic-0. The reverse of this action is obtained when the input is at logic-1. When the DISABLE INPUT control is set to logic-1, both Q1 and Q2 are driven OFF, irrespective of the state of the IN input, and under this condition, OUT is effectively disabled, and acts as an open circuit. Figure 13 shows the simplified equivalent circuit of this buffer when it is in its high-impedance output state.
FIGURE 13. Equivalent of a three-state buffer circuit in its third high-impedance state.
The third CMOS circuit variation is that of the ‘bilateral switch’ or transmission gate. The basic action of any enhancement-mode IGFET is such that its drain-to-source path acts like a near-perfect unidirectional switch: When the IGFET is OFF, the path acts like an open circuit, and when it is ON, it acts like a low-value resistor and (unlike a bipolar transistor) does not suffer from saturation-voltage problems, etc. When turned on, an n-channel IGFET passes current from drain-to-source, and a p-channel IGFET passes current from source-to-drain. Thus, a near-perfect bidirectional or bilateral electronic switch can be made by wiring an n-channel and a p-channel IGFET in parallel (source-to-source and drain-to-drain) and driving their gates in anti-phase, as shown in Figure 14.
FIGURE 14. Basic CMOS bilateral switch or transmission gate.
Here, both IGFET paths are effectively open when the CONTROL input is at logic-0, and closed when the CONTROL input is at logic-1. Under the closed condition, current can flow from X to Y via Q1, or from Y to X via Q2; current can thus flow in either direction between these points, and the circuit thus simulates a simple electro-mechanical switch.
CMOS Basic Usage Rules
CMOS ICs are very easy to use. They are very tolerant of supply voltage variations and, unlike TTL types, present very few input-drive/output-drive matching problems. There are, in fact, only seven basic usage themes to consider when dealing with CMOS which are: Type selection; Handling CMOS; Power supplies; Input signals; Unused inputs; and Interfacing.Type Selection
The question “Which CMOS family should I use?” can easily be answered with the help of Figure 15, which lists the major characteristics of the six readily-available modern CMOS sub-families and compares them with those of LS TTL. Of these types, the 4000UB sub-family is only available in the form of a few simple buffer and inverter ICs, and should be regarded as a simple variant of the main 4000B sub-family. The 74HCT and 74ACT types are meant to be directly driven from TTL outputs, and are of use only in a few specialized applications.
FIGURE 15. Table showing general characteristics of LS TTL and the six major CMOS digital IC types.
Of the remaining three CMOS sub-families (4000B, 74HC, and 74AC), the 4000B sub-family can be used in any application that requires the use of a supply in the range of 3V to 15V and in which maximum operating frequencies do not exceed 2 MHz at 5V, or 6 MHz at 15V. Alternatively, if supply voltages are restricted to the 2V to 6V range, the 74HC sub-family can be used to operate at frequencies up to 40 MHz at 5V, or the 74AC sub-family at frequencies up to 100 MHz at 5V.
Note that all TTL ICs have special input-drive requirements, and the fan-out numbers in Figure 15 show how many parallel-connected standard LS TTL inputs can be directly driven from the output of each listed sub-family member. Thus, 4000B CMOS can only drive one such input, but 74HC and HCT CMOS can each drive 10 such inputs, and 74AC and ACT can each drive up to 60 LS TTL inputs.
Handling CMOS
CMOS is based on high-impedance IGFET technology, which — when being handled — is easily damaged by high-voltage static charges of the type that can build up on the body of the person handling them. All modern CMOS digital ICs incorporate extensive internal diode-clamping circuitry that is designed to protect their internal IGFETs against damage from reasonable amounts of this type of static discharge when the IC is being handled.
Figure 16(a) shows the basic laboratory circuit that is used — when testing CMOS ICs — to simulate reasonable values of static discharge from a human body; C1 has a value of 100 pF and simulates the typical body capacitance of a charged human adult, and R1 has a value of 1.5K and simulates the body’s typical discharge resistance. When a CMOS IC is being given evaluation tests, C1 is charged to a high-value test voltage via S1, and is then applied to two of the IC’s test points via S1 and R1. A basic CMOS element has four terminals (IN, OUT, V+, and 0V), and thus has a total of 12 possible two-pin test permutations. The test circuit is applied to each of these two-pin permutations in a full test sequence. Typically, modern CMOS digital ICs are expected to survive a test voltage of 2.5 kV in all of these test modes.
FIGURE 16. (a) Typical electrostatic discharge test circuit, and (b) simple equivalent of a CMOS digital IC element.
Figure 16(b) shows the basic form of a CMOS element’s internal protection circuitry. Here, D1 or D2 conduct if IN tries to go above V+ or below 0V; D3 or D4 conduct if OUT tries to go above V+ or below 0V. D5 conducts if 0V tries to go above V+; D5 also conducts in the zener mode if V+ goes more than about 20V above 0V.
It is important to understand the meaning of these CMOS static discharge protection tests. Suppose that a 3 kV test voltage is applied between the IC’s reverse-connected 0V and V+ pins. Under this condition, D5 is forward biased, and C1 discharges via D5 and R1; R1 limits C1’s peak discharge current to 2A and gives it a basic time constant of 150 nS. Thus, D5 passes only a very brief spike of forward current as C1 discharges. If D1’s thermal time constant is very long compared to the period of the spike, it may not suffer damage from this test, even though it can only handle normal DC currents of (say) 25 mA maximum. Note that the peak voltage appearing across D5 in this test is roughly 1V; most of C1’s 3 kV discharge voltage is lost across R1.
The protection networks used in CMOS ICs are not designed to be effective against massive values of static discharge, such as the several thousand volts that may be generated by a person vigorously prancing about on a nylon carpet, etc. Consequently, when handling naked CMOS ICs, always take sensible precautions against the build-up of large static charges. Do not wear nylon clothing or use nylon mats/carpets in the workshop, and make sure that soldering irons, etc., are correctly grounded.
To be really safe, wear a grounded metal wrist strap when working with CMOS, particularly when soldering. Note, however, that in reality it is very unlikely that you will ever damage a CMOS IC in normal handling, even if you are foolish enough not to wear a grounded wrist strap.
Power Supplies
CMOS ICs of the 4000B and 74HC and 74AC types are designed to operate over a wide range of supply voltages, and can thus be powered from batteries or from regulated or unregulated power supplies. 74HCT and 74ACT types, however, are designed to operate from supplies in the 4.5V to 5.5V range, and must be powered from low-impedance, well-regulated supplies of the types shown in Figures 1 to 3 of last month’s article.
All CMOS ICs generate fast pulse-switching edges. Consequently, most CMOS circuits should be used with a PCB that is designed to give excellent high-frequency supply decoupling to each IC. In general, the PCB’s supply and ground-rail tracks must be as wide as possible (ideally, the 0V track should take the form of a ground plane), all connections and inter-connections should be as short and direct as possible, the PCB’s supply rails should be liberally sprinkled with 4.7 µF Tantalum electrolytic capacitors (at least one per 10 ICs) to enhance l.f. decoupling, and with 10 nF disk ceramics (at least one per four ICs, fitted as close as possible between an IC’s supply pins) to enhance h.f. decoupling.
When experimenting with CMOS ICs, never allow the power supply to be connected in the wrong polarity, since this will cause heavy supply currents to flow through the IC’s protective diode networks (specifically, through D5 in Figure 16) and cause instant damage to the IC’s substrate.
Input Signals
When using CMOS, all IC input signals must — unless the IC is fitted with a Schmitt-type input — have very sharp rising and falling edges. If rise or fall times are too long, they may allow the input terminal to hover in the CMOS element’s linear zone long enough for the element to burst into wild oscillations and generate spasmodic output signals that may disrupt associated circuitry (such as counters and registers, etc). If necessary, slow input signals can be converted into fast ones by feeding them to the IC’s input terminal via CMOS Schmitt elements.
One possible way of damaging CMOS is via a very low impedance input or output signal that is either connected to the CMOS when its power supply is switched off, or is of such large amplitude that it forces the input terminal well above the positive supply line or below the zero-volts rail, thus causing a damaging current to flow through one or more of the IC’s protection diodes (specifically, through Figure 16’s input diodes D1 or D2, or output diodes D3 or D4). The possibility of such damage can be eliminated by wiring a 1K resistor in series with each input/output terminal to limit such currents to safe values of a few milliamps.
Unused Inputs
Unused CMOS input terminals must never be allowed to simply float, but must always be tied to definite logic levels by either connecting them directly to the supply or ground rails (depending on the IC’s logic requirements), or to some other point with well defined logic levels. Figure 17 shows some of the available options.
FIGURE 17. Alternative ways of connecting unwanted CMOS inputs (see text).
If the unwanted input is on a multi-input gate, it can be disabled by shorting it to one of the gate’s used inputs, as in Figure 17(c), where a three-input AND gate is shown used as a two-input type. If the IC is a multiple gate type in which an entire gate is unwanted, the gate should be disabled by tying all of its inputs to a common high or low point, as in (d) and (e).
All used CMOS input terminals must also be tied to definite logic levels, and must never be allowed to float. Figure 18 shows three commonly used options.
FIGURE 18. All used CMOS inputs must be tied to definite logic levels (see text).
In (a), the input is normally tied low by R1, and in (b) it is normally tied high by R1. In (c), the input is direct-coupled to the output of a driving stage, which determines the input logic level.
Interfacing
An interface circuit is one that enables one type of system to be sensibly connected to a different type of system. In a purely CMOS system, in which all ICs are designed to connect directly together, interface circuitry is usually needed only at the system’s initial input and final output points, to enable them to merge with the outside world via items such as switches, sensors, relays, and indicators, etc.
Occasionally, however, CMOS ICs may be used in conjunction with other logic families (such as TTL), in which case an interface may be needed between the different families. Thus, as far as CMOS is concerned, there are three basic classes of interface circuit, which are: Input interfacing, Output interfacing, and Logic family interfacing.
Input Interfacing
The digital signals arriving at the inputs of a CMOS system must be clean ones with well-defined logic levels and with fast rise and fall times. It is the input interfacing circuitry’s task to convert external input signals into this format. Figures 19 to 22 show four simple examples of such circuitry; these circuits are similar to the TTL designs shown in last month’s Figures 6 to 9, but must use CMOS Schmitt elements and can use any positive supply rail voltage within the operating limits of the CMOS element.
The Figure 19 circuit is designed to clean up the dirty switching signals of push-button switch SW1 and convert them into a form suitable for driving a normal CMOS input. Here, the input of the Schmitt buffer is tied to ground via R1 and R2 and is normally low. When SW1 is closed, C1 rapidly charges up and drives the Schmitt output high, but when SW1 opens again, C1 discharges relatively slowly via R1, and the Schmitt output does not return low again until roughly 20 mS later. The circuit thus ignores the transient switching effects of SW1 noise and contact bounce, etc., and generates a clean output switching waveform with a period that is roughly 20 mS longer than the mean duration of the SW1 switch closure.
FIGURE 19. CMOS noiseless push-button switch.
Figure 20 shows a circuit that can be used to interface almost any clean digital signal to a normal CMOS input. Here, when the input signal is below 500 mV (Q1’s minimum turn-on voltage), Q1 is cut off and the inverting Schmitt’s output is at logic-0. When the input is significantly above 600 mV, Q1 is driven on and the Schmitt output goes to logic-1. Note that the digital input signal can have any maximum voltage value, and R1 is chosen to simply limit Q1’s base current to a safe value.
FIGURE 20. CMOS transistor input interface.
Figure 21 is a simple variation of the above circuit, with the transistor built into an optocoupler; the circuit action is such that the Schmitt’s output is at logic-0 when the optocoupler input is zero, and at logic-1 when the input is high; note that the optocoupler provides total electrical isolation between the input and CMOS signals.
FIGURE 21. CMOS optocoupler input interface.
Finally, Figure 22 is another simple circuit variation, with the basic digital input signal fed to Q1’s base via the R1-C1-R2-C2 low-pass filter network, which eliminates unwanted high-frequency components and thus can convert very dirty input signals (such as those from vehicle contact-breakers, etc.) into a clean CMOS format.
FIGURE 22. CMOS dirty-switching input interface.
Output Interfacing
CMOS totem-pole output stages are designed to source or sink fairly high peak values of output current. Consequently, if the output is shorted directly to the IC’s zero-volts or positive supply rail, the resulting DC output currents can, in some cases, be so high that the IC may be damaged. Thus, when a CMOS IC is used to drive a DC load, its load current must always be limited to a safe value.
Figure 23 shows the typical short circuit output currents of two different manufacturer’s 4000B-series CMOS output stages over the 5V to 15V operating voltage range. In practice, the maximum DC values of these output loads must be limited to 10 mA of current or 100 mW of power dissipation, whichever is the lower of these values.
FIGURE 23. Typical 4000B-series short-circuit output currents (at 25 OC).
Figure 24 shows the typical short-circuit output currents of standard and bus driver versions of 74HC-series CMOS output stages over the 2V to 6V operating voltage range. In practice, the maximum DC values of these currents must be limited to 25 mA in standard HC types, and 35 mA in bus driver HC types.
FIGURE 24. Typical 74HC series short-circuit output currents (at 25 OC).
The only time this current limiting matter is likely to present any real problem is when using CMOS to drive some type of LED load (including those at the inputs of optocouplers, etc.). Figures 25 and 26 show basic ways of driving an LED via non-inverting or inverting CMOS elements.
FIGURE 25. LED-driving output interface, using non-inverting CMOS elements.
FIGURE 26. LED-driving output interface, using inverting CMOS elements.
Note in these circuits that R1 sets the LED’s ON current, and has a value of [(V+ - Vs)/I] - Rx, where V+ is the supply voltage, Vs is the LED’s saturation voltage (typically 2.0 to 2.5 volts), I is the LED’s ON current (in amps), and Rx is the CMOS elements saturation resistance (and varies widely with voltage, current, and with individual ICs).
Typically, however, Vs equals 2.2V, and Rx has an approximate value of 100Ω in a standard 74HC output or 70Ω in a bus driver output, or 500Ω in a standard 4000B output. Thus, to set the LED current at 10 mA, R1 needs a value of about 180Ω in a 5V standard 74HC circuit, 220Ω in a 5V bus driver 74HC circuit, 270Ω in a 10V 4000B circuit, or 820Ω in a 15V 4000B circuit.
Note that CMOS outputs can be used to drive any of the basic TTL output interface circuits shown in Figures 12 to 17 in the last installment (Part 3) of this series by simply wiring a current-limiting resistor in series with the CMOS output, to limit its output current to a safe value.
Logic Family Interfacing
It is generally bad practice to mix different logic families in any system, but on those occasions where it does occur, the mix is usually made between TTL and CMOS devices. Figures 18 to 23 of last month’s article showed six basic ways of interfacing TTL and CMOS ICs. Note that 74HCT and 74ACT types of CMOS ICs are designed to be directly driven from TTL outputs, without need for special interfacing methods. Also note that standard 4000B-series and 74CXX-series CMOS elements have very low fan-outs and can only drive a single standard TTL or LS TTL element, but 74HCXX-series (and 74ACXX-series) CMOS elements have excellent fan-outs and can directly drive up to two standard TTL inputs, or 10 LS TTL inputs, or 20 ALS TTL inputs.
Most TTL ICs with open-collector (OC) outputs have output-voltage ratings of at least 15V (but the main IC has a normal 5V rating), and can be interfaced to the input of a CMOS logic IC by using the connections shown in Figure 27.
FIGURE 27. TTL (open collector output) to CMOS interface, using common or independent +ve rails.
Here, R1 acts like a pull-up resistor, and the CMOS IC can either share the 5V supply of the TTL IC, or can use its own 5V to 15V positive supply rail. Similarly, a CMOS IC with an open-drain (OD) output can be interfaced to a normal TTL input by using the connections shown in Figure 28 but, in this case, the two ICs must share a common 5V supply rail.
FIGURE 28. CMOS (open drain output) to TTL interface.
CMOS Supply Pin Notations
Most digital ICs have only two supply pins, one of which connects to a circuit’s positive supply rail, and the other to the zero volts rail. In TTL ICs, these pins are conventionally notated VCC and GND respectively, with the VCC notation implying that the positive rail usually connects to the collector sides of the IC’s internal transistors.When 4000-series CMOS ICs were first introduced, the supply pins were renamed VDD and VSS respectively, implying that the positive rail usually connects to the drain side of the IC’s internal IGFETs, and the zero-volts rail to the source sides. These notations are, in fact, quite ambiguous, but are still widely used in CMOS manufacturer’s data books.
When CMOS was first used as a C sub-family in the 74-series range of ICs, its supply pins were renamed VCC and GND, to comply with normal TTL conventions, and this system has subsequently been used on all other CMOS sub-families used in the 74-series of ICs. In recent times this same system has started to be used on the 4000-series of CMOS ICs, as well, and the current situation is that a CMOS IC positive supply terminal may be notated VCC or VDD, depending on the whim of the individual manufacturer.
Q . IIIIII S2 Speed & Power in Logic Families
The previous Supplemental Chapter dealt with static parameters ("DC characteristics") of voltage and current for digital chips. This chapter on dynamic parameters extends our look at data sheets to what are called "AC characteristics"-various propagation delays and timing requirements. We also look at the relationship between power consumption and switching speed. In the process it is necessary to compare various semiconductor versions of logic gates. The marketplace has provided an environment for a struggle between different versions of logic chips. Over the years some logic families have survived the struggle and thrived, while others have become virtually extinct. In this chapter we examine the surviving families, and study their evolution. We see what virtues the survivors possess-chief among these are fast switching speed, low power consumption, high packing density and reasonable cost per gate. To proceed, you may want to review facts of electric circuits with energy-storing capacitors-including what an RC time constant is.
S2 / 1 The virtue of speed
Back in 1987 an IBM RT workstation could load my desktop publishing program INTERLEAF from hard disk to main memory in 40 seconds. After a central processing unit (CPU) upgrade in 1988 the RT could load the same benchmark program in 30 seconds. Why the reduction in loading time? The hard disk hadn't been changed, so the reduction must have come from improvements in the CPU. While there may have been some advances in the CPU's "architecture"-notably more parallel processing and better direct memory access (DMA)-a major improvement was in the shorter propagation delays of individual gates and chips. Faster hardware is better, all other things being equal. We'll see in this chpt. that one of the other "things" is the power required to increase speed, and that extra power consumption, and the concomitant heat generated, may be a cost which out-weighs speed improvement.
Our first goal in this chapter will be to understand timing parameters in data sheets of chips. We want not so much to delve into the chip fabrication technology which brings about greater speed as to appreciate the limitations which timing parameters place on circuit design.
S2 / 1 / 1 Propagation delay
When an output switches from one state to the other, propagation delay t-p is counted as the time from "instantaneous" input change to time of output reaching a new logic level, either VOL or VOH, as illustrated below. We saw a figure like this one in the beginning of §5, when rise time and transport time were added up to account for flip flop feedback delay.
Propagation delay of a gate is not the same thing as rise or fall time for an individual transistor. To propagate through an IC a signal may have to pass through several transistors and may pass through different transistor paths depending on the kind of input (data, select, enable, etc) being asserted.
Propagation delay of a gate is not the same thing as rise or fall time for an individual transistor. To propagate through an IC a signal may have to pass through several transistors and may pass through different transistor paths depending on the kind of input (data, select, enable, etc) being asserted.
An npn bipolar transistor can turn on faster than it can turn off, which results in 7400 series chips having different propagation delays for LO-to-HI and HI-to-LO output transitions. MOS transistors have a similar asymmetry-for a given channel width n-channel MOS transistors are faster than p-channel MOS transistors.
S2#1--wire delay and RC time constant problem
S2 / 1 / 2 BOX: What causes propagation delay in logic circuits?
A small amount of delay in signal transmission is unavoidable because of the finite speed of light, which travels one foot per nanosecond (signals move in wire at nearly the speed of light). But most delay in switching circuits is due to the time it takes charges stored in one place to move to another. The removal of stored charge from a capacitor through a resistance to "ground" takes time, in the same way that emptying a bathtub through the drain takes time.
Electronic switches are made of transistors. Consider the input side of a common-emitter transistor circuit, and the case of turning it off-charge caught in the base region must be removed before the flow of current from collector to emitter is stopped. To a certain approximation the base-emitter junction of a transistor acts like a capacitor.
When a bipolar transistor-inverter is ON sufficient base current can "saturate" the device and fill its base region with electrons. The good news about saturation is that it lowers the collector-to-emitter voltage-which represents logical LOW-to about
0.15v = VCEsat;
this lower output (VOL) means a good high level noise margin. The bad news is that a saturated bipolar transistor takes time to turn OFF. It takes extra time to remove charge from the thin base region. The region can be modeled by a parasitic junction capacitance, shown in the figure below. The junction capacitance must be charged or discharged to or from 0.6v, in order to complete switching. Remember Q=CV, where Q is charge, C is capacitance and V is voltage.
When base current stops flowing the transistor will still allow IC to pass (through the base, to the emitter, as electron "minority carriers" in npn) so long as "majority" charge is stored in the base. In one case, the excess stored charge in the base will be removed by "recombination of minority and majority carriers," a process which can take many nanoseconds. In another, the excess base charge may flow out through the resistor RB.
0.15v = VCEsat;
this lower output (VOL) means a good high level noise margin. The bad news is that a saturated bipolar transistor takes time to turn OFF. It takes extra time to remove charge from the thin base region. The region can be modeled by a parasitic junction capacitance, shown in the figure below. The junction capacitance must be charged or discharged to or from 0.6v, in order to complete switching. Remember Q=CV, where Q is charge, C is capacitance and V is voltage.
When base current stops flowing the transistor will still allow IC to pass (through the base, to the emitter, as electron "minority carriers" in npn) so long as "majority" charge is stored in the base. In one case, the excess stored charge in the base will be removed by "recombination of minority and majority carriers," a process which can take many nanoseconds. In another, the excess base charge may flow out through the resistor RB.
Saturation can be prevented by placing a Schottky diode from base to collector:
When the transistor is ON the Schottky diode diverts some of the RB current formally headed for the base, and "clamps" the base-to-collector voltage at about 0.3v, instead of the higher 0.5v. VCE is about 0.3v [and this slightly higher collector voltage reduces the DHL noise margin by 0.1v.]
When the transistor is ON the Schottky diode diverts some of the RB current formally headed for the base, and "clamps" the base-to-collector voltage at about 0.3v, instead of the higher 0.5v. VCE is about 0.3v [and this slightly higher collector voltage reduces the DHL noise margin by 0.1v.]
S2#2--role of R sub L in switching speed of inverter
Another way to lower propagation delay-Decrease resistances around the chip-but if RB is reduced too much then IB will reach a dangerously high level and might burn out the transistor.
On the output side of a chip, capacitance associated with the load can increase delay in transmission.
How is propagation delay decreased in CMOS? By reducing the "channel length." In advanced CMOS, channel length can be fabricated at less than one micron.
S2 / 1 / 3 Delay in combinational gates
Propagation delay time is tP. For a combinational gate with one kind of input, like a NAND gate on a 7400 chip, delay on data sheets is listed as tPLH and tPHL-the delay from input to low-to-high or high-to-low OUTPUT switching. Sometimes data sheets list only maximum values for each of these propagation delays, and in the case of the 7400 chip the values are
7400 tPLH for input to output 22 nsec, maximum
tPHL for input to output 15 nsec
Other variations for propagation delay in data sheets are minimum and typical. Usually a designer is worried about the worst-case time, which, for a combinational chip, is the maximum delay. Sometimes a minimum delay is cause for concern, to prevent race conditions in flip flop circuits. Notice that the transistor turning off (tPLH) is associated with the longer propagation delay; tPLH > tPHL .
7400 tPLH for input to output 22 nsec, maximum
tPHL for input to output 15 nsec
Other variations for propagation delay in data sheets are minimum and typical. Usually a designer is worried about the worst-case time, which, for a combinational chip, is the maximum delay. Sometimes a minimum delay is cause for concern, to prevent race conditions in flip flop circuits. Notice that the transistor turning off (tPLH) is associated with the longer propagation delay; tPLH > tPHL .
For other chips, with several kinds of input, there can be more timing parameters. The 24 pin Texas Instruments "multiport video dynamic RAM" chip 4461 lists in its data sheets 73 timing parameters, mostly as minimum values, but in some cases as minimum and maximum. The 73 timing parameters are explained with the help of 18 timing diagrams! You can see the varieties of timing in the DDZO chapter 8, Memory.
Propagation delay can have meaning for more than a single chip. It can be measured or calculated for a hardware system with various data paths. The designer may have to search for minimum and maximum delays. Maximum delay paths through digital systems are called critical paths.
S2#3--interpreting data sheet AC parameters for MUX
S2 / 1 / 4 Flip flop timing
An un-clocked SR flip flop is graded by the propagation delay from SET or RESET to changed output. SET or RESET must be on for a minimum duration of tW. Examples of flip flop timing parameters are shown below for a clocked D flip flop with asynchronous SET.
In edge-triggered flip flops we know from §5 that data input must meet set-up and hold times with respect to the clock edge, as shown above. In flip flops with both synchronous and asynchronous inputs, a parameter tREC, recovery time, can be defined which measures the amount of time after a SET or RESET that a CLOCK pulse will be recognized. A single parameter that somewhat summarizes the performance of a clocked flip flop is fMAX, the maximum clock rate in Hertz the chip can handle before errors occur.
In edge-triggered flip flops we know from §5 that data input must meet set-up and hold times with respect to the clock edge, as shown above. In flip flops with both synchronous and asynchronous inputs, a parameter tREC, recovery time, can be defined which measures the amount of time after a SET or RESET that a CLOCK pulse will be recognized. A single parameter that somewhat summarizes the performance of a clocked flip flop is fMAX, the maximum clock rate in Hertz the chip can handle before errors occur.
Example 1. Timing parameters for a 74F74 D flip flop are given below:
S2 / 2 Power consumption
Designers of electronic logic gates (IC's) fight with the tendency of switching circuits to use more power the faster they switch. Why the concern about power consumption?
(1) Need for a larger power supply, and the cost of the power from the electric company. If the unit is not plugged in, batteries will drain more quickly the more power consumed per chip.
(2) Power consumed by a chip ends up as heat. Because heat degrades the performance of an IC, and enough heat can burn it out, cooling systems must be installed where too much heat will be generated.
(1) Need for a larger power supply, and the cost of the power from the electric company. If the unit is not plugged in, batteries will drain more quickly the more power consumed per chip.
(2) Power consumed by a chip ends up as heat. Because heat degrades the performance of an IC, and enough heat can burn it out, cooling systems must be installed where too much heat will be generated.
S2 / 2 / 1 Box: Defining power
What is Power? Power = energy / sec.
Recall from mechanics that energy (or work) is force x distance.
Example 2. A 7 kg mass bowling ball slowly raised 0.5 meter against a gravitational force gains 7 x 9.81 x ½ = 3.5 joules of energy.
Where 9.81 is the gravitational constant in MKS units.
In electricity, F = q·E, where E is the electric field vector. An electron with a charge of -1.6x10-19 coulombs moved slowly ½ meter against an electric field of 1 volt/meter gains 1.6x10-19 x ½ = 8x10-18 joules of energy.
Recall from mechanics that energy (or work) is force x distance.
Example 2. A 7 kg mass bowling ball slowly raised 0.5 meter against a gravitational force gains 7 x 9.81 x ½ = 3.5 joules of energy.
Where 9.81 is the gravitational constant in MKS units.
In electricity, F = q·E, where E is the electric field vector. An electron with a charge of -1.6x10-19 coulombs moved slowly ½ meter against an electric field of 1 volt/meter gains 1.6x10-19 x ½ = 8x10-18 joules of energy.
Power is the rate of energy production or consumption. If U(t) is the energy of a system at time t, then power is dU/dt, measured in joules/sec, or watts. Power can either be generated or consumed by a system. The power company and a "power supply" are aptly named, although a power supply normally transforms AC into DC, and is not a primary generator of electrical power, as the rotating machinery of a power plant is.
As you may know, to compute power consumed in an electrical component, multiply voltage across the component times current flowing through. The diagram below shows the voltage and current conventions for positive power absorbed by a resistor:
Below the formula for power in terms of current and voltage is developed.
We include a time parameter in the power formula as a reminder that power can be an instantaneous quality. To compute steady-state or DC or average power consumed by a chip, multiply supply voltage VCC by supply current ICC. Supply current is listed in the data sheet for a chip under "DC" or static characteristics; it is usually listed two ways, ICCL, and ICCH. ICCL is the current which flows into the chip when all inputs are connected to LO; ICCH is for all inputs connected HI.
As you may know, to compute power consumed in an electrical component, multiply voltage across the component times current flowing through. The diagram below shows the voltage and current conventions for positive power absorbed by a resistor:
Below the formula for power in terms of current and voltage is developed.
We include a time parameter in the power formula as a reminder that power can be an instantaneous quality. To compute steady-state or DC or average power consumed by a chip, multiply supply voltage VCC by supply current ICC. Supply current is listed in the data sheet for a chip under "DC" or static characteristics; it is usually listed two ways, ICCL, and ICCH. ICCL is the current which flows into the chip when all inputs are connected to LO; ICCH is for all inputs connected HI.
Example 3. The 7400 quad NAND gate the Signetics data sheet shows
7400 74LS00
ICCL = 8.0 mA 1.6 mA, maximum, and
ICCH = 12 mA 4.4 mA, maximum
where LS stands for "low-power Schottky."
Below are two circuits for showing ICCH (a) and ICCL (b).
static, dynamic power.
Data sheets for a chip list ICC, supply current for a chip with the understanding of no load on the output pins. If VCC is 5 volts, then power, in watts, is
5 x ICC = Power consumed by the chip.
Connect the ammeter between the power supply and the chip to monitor ICC.
7400 74LS00
ICCL = 8.0 mA 1.6 mA, maximum, and
ICCH = 12 mA 4.4 mA, maximum
where LS stands for "low-power Schottky."
Below are two circuits for showing ICCH (a) and ICCL (b).
static, dynamic power.
Data sheets for a chip list ICC, supply current for a chip with the understanding of no load on the output pins. If VCC is 5 volts, then power, in watts, is
5 x ICC = Power consumed by the chip.
Connect the ammeter between the power supply and the chip to monitor ICC.
Example 4. How many 7400 chips would it take to [change a light bulb?] consume the same power as a 100 watt light bulb? The data sheet for a 7400 chip lists
ICCH at 12mA = 12 x 10-3 amps,
so each chip consumes 5 x 12 x 10-3 = 0.06 watts. 100 0.06 1600 chips!
Actually, the voltage supplied to a light bulb is of the form V(t) = 170 cos (2p60·t) volts;
110 volts is the root-mean-square value of V(t). The time-varying voltage from the power company is converted to steady ("DC") voltage in a power supply.
ICCH at 12mA = 12 x 10-3 amps,
so each chip consumes 5 x 12 x 10-3 = 0.06 watts. 100 0.06 1600 chips!
Actually, the voltage supplied to a light bulb is of the form V(t) = 170 cos (2p60·t) volts;
110 volts is the root-mean-square value of V(t). The time-varying voltage from the power company is converted to steady ("DC") voltage in a power supply.
When a power supply delivers power to its output ports it is an active device or system; a passive device, like a resistor, absorbs power. The figure below shows conventions for
Integrated circuit chips are power-absorbing devices. A passive device which absorbs power gets warm. A light bulb absorbs power from the power company and radiates a little light and a lot of heat.
Some chips, particularly display drivers like the 7448 , may get hot to the touch because they're consuming a lot of power for their small size, sending current out to display segments-an "8" signal should feel hotter than a "1."
Integrated circuit chips are power-absorbing devices. A passive device which absorbs power gets warm. A light bulb absorbs power from the power company and radiates a little light and a lot of heat.
Some chips, particularly display drivers like the 7448 , may get hot to the touch because they're consuming a lot of power for their small size, sending current out to display segments-an "8" signal should feel hotter than a "1."
Dynamic power dissipation-The charge stored on a capacitor is C·V, where V is the voltage across the plates. Imagine moving the charge on a load capacitor CL as the output changes from 0 to VCC. The average voltage the charges will see is ½VCC, and the total amount of charge moved will be CL·VCC. Since voltage is the energy required to move a unit charge across the capacitor, the total energy stored in the capacitor is ½ CL·(VCC)2. If the output switches at a rate* f per second, then the power, or energy per second, dissipated by the switch is
f·CL·(VCC)2 called dynamic power dissipation.
[reference: Sedra & Smith, 3rd Edition, p. 914]
For TTL gates the dynamic power dissipation is not appreciable compared to the static power dissipation until high frequency (MHz) rates of switching are seen. For CMOS gates dynamic power dissipation is the main form of power dissipation; power consumed by a CMOS chip is almost linear with frequency of switching.
f·CL·(VCC)2 called dynamic power dissipation.
[reference: Sedra & Smith, 3rd Edition, p. 914]
For TTL gates the dynamic power dissipation is not appreciable compared to the static power dissipation until high frequency (MHz) rates of switching are seen. For CMOS gates dynamic power dissipation is the main form of power dissipation; power consumed by a CMOS chip is almost linear with frequency of switching.
Electrical power runs the world.
Delay-power product. Multiply [power x time] and units of energy result. Multiply the delay (time per state switch) and power consumed by chip, and you have energy used per state switch. For example, a 7400 chip has a maximum delay-power DP product of about 20 nanoseconds x 5v x 10 mA = 1000 pico Joules, while a 74LS00 has a maximum DP of 150 pJ.
Relationship between power & speed. If you inspect data sheets of chips from different logic families, you'll find that switching speed increase is generally accompanied by an increase in current delivered to the chip. For example,
chip ICCL tPHL DP product
7400 12 mA 15 ns 900 pJ
74S00 36 mA 5 ns 900 pJ
The 7400 uses less current but switches more slowly than the 74S00, but both chips have the same DP product. Low-power Schottky chips have considerably lower DPs and so are to be preferred over regular TTL and plain high speed Schottky chips.
chip ICCL tPHL DP product
7400 12 mA 15 ns 900 pJ
74S00 36 mA 5 ns 900 pJ
The 7400 uses less current but switches more slowly than the 74S00, but both chips have the same DP product. Low-power Schottky chips have considerably lower DPs and so are to be preferred over regular TTL and plain high speed Schottky chips.
Heat. The generation of heat would not be a matter of concern to us were it not for the fact that semiconductor switches can be destroyed by high temperatures. Why does heat damage chips? Semiconductor crystals are created at 1200°C, so who cares if power consumption on a chip turns up the temperature a few hundred degrees? In commercial IC devices, however, aluminum is used as a metallization layer for routing of wire-like connections. Aluminum in contact with silicon melts at around 550°C; the melted metal can cause a short circuit through a junction, or it can be plastically distorted to become an open circuit. Since local temperature can be higher than the average temperature, aluminum spiking can occur before the chip temperature reaches 500°C. There's not really much disruption of the semiconductor crystal structure from excess heat in chips.
Electrostatic-not heat-damage to CMOS can cause a filament of metal to blast through a junction, and thereby produce a local short circuit. Catastrophic failure from heat is not the only concern. Higher temperatures can cause chips to operate at slower speeds.
Texas Instruments, "Manufacturing Process of Integrated Circuits: Sand to Circuit," a 40 min. VHS color video tape (1991).
In some cases, such as processing radar or video in real time, the fastest chips obtainable must be used, and the costs in power consumed, heat generated and circuits artificially cooled must be paid.
Think of the heat generated by the muscles of the animals below.
from The Far Side Gallery 3, by Gary Larson
from The Far Side Gallery 3, by Gary Larson
S2 / 3 Families and super-families
In a narrow sense a logic family is a set of small and medium-scale integrated circuits, fabricated from a common process, which span the range of gates and flip flops that a logic designer may find useful in assembling a large digital system. Like Classic Coke mutating into New Coke, Diet Coke, Cherry Coke and Caffeine-free Coke, successful logic families evolve new sub-groups and become super-families. Only two digital logic technologies are in the super-family category: transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS). TTL was not the first logic family, but by the late 60's chips in the 7400 series had a combination of shorter propagation delay and lower power consumption, compared to the now obsolete families of diode logic, resistor-transistor logic, and diode-transistor logic. TTL chips in dual in-line packages (DIPs) filled the circuit boards of computers.
CMOS started out in the 1970's as the 4000 series family, but its virtue of low static power consumption, and breakthroughs in speed thanks to narrow channel fabrication, have allowed CMOS to become the technology of choice for highly integrated circuits. In 1991 CMOS is the most widely used digital logic process. The CMOS process is applied widely to memories, microprocessors and gate arrays-the kinds of "LSI" chips not generally considered in a particular logic family.
S2 / 3 / 1 The TTL super-family
In 1965 TTL was the first process technology able to be fashioned into integrated circuits which had a good combination of high speed and low power consumption. TTL is a bipolar process in which npn transistors operate mostly in the "saturated" and "cutoff" regions of their operating curves. Below we list delay and power dissipation specs of various TTL families.
7400, 74L00, and 74H00 chips are "gold-doped" in the fabrication process; all chips with "S" is the letter designation have Schottky diodes from base to emitter on transistors which can saturate. In the lettering scheme, "L" stands for low-power, "H" stands for high speed, "F" stands for fast, and "A" stands for "advanced."
7400, 74L00, and 74H00 chips are "gold-doped" in the fabrication process; all chips with "S" is the letter designation have Schottky diodes from base to emitter on transistors which can saturate. In the lettering scheme, "L" stands for low-power, "H" stands for high speed, "F" stands for fast, and "A" stands for "advanced."
[Propagation delay the average of tPHL and tPLH; power consumption = 5 x ½(ICCH + ICCL)]
All 74 TTL families are shadowed by 5400 families which meet military specifications for wider tolerance to temperature variation.
Sample costs in 1991: 74LS00 31¢, 7400 36¢, 54LS00 69¢; [74L and 74H series, obsolete.]
In 1965 a 7400 chip cost around $20!
All 74 TTL families are shadowed by 5400 families which meet military specifications for wider tolerance to temperature variation.
Sample costs in 1991: 74LS00 31¢, 7400 36¢, 54LS00 69¢; [74L and 74H series, obsolete.]
In 1965 a 7400 chip cost around $20!
S2 / 3 / 2 The CMOS super-family
Once just another member of the MOS group, CMOS has become a super-family of its own. In the 1970's the original appeal of CMOS, compared to TTL, was its low power consumption and wide tolerance for power supply voltages. CMOS chips filled a niche in battery-operated devices, where voltage would slowly decline over the life of the battery. The first CMOS family, the 4000-series chips, averaged just nanowatts quiescent power per gate and tolerated voltages as low as 3 and as high as 18 volts for VCC.
- CMOS families: speed, power, noise, fanout...
4000, 14000 (Motorola)
B - series
74C00 same pinout as 7400 TTL series
74HC00 H for "high speed"
74HCT00 for interface to TTL chips
74AC00 "advanced"
74ACT for interface to TTL chips
B - series
74C00 same pinout as 7400 TTL series
74HC00 H for "high speed"
74HCT00 for interface to TTL chips
74AC00 "advanced"
74ACT for interface to TTL chips
see Advanced CMOS Logic, Designer's Handbook, TI, 1988.
and High Speed CMOS Data Book, TI, 1989.
CMOS Logic Data , Motorola, 1990.
See Wakerly, page 129 for 1989 CMOS data table.
and High Speed CMOS Data Book, TI, 1989.
CMOS Logic Data , Motorola, 1990.
See Wakerly, page 129 for 1989 CMOS data table.
CMOS logic and propagation delay. MOS stands for "Metal-Oxide-Semiconductor," and is a description of the top-to-bottom layers in a MOS chip. The oxide is silicon dioxide, a hard insulating material. The metal is in the form of thin interconnecting strips from one gate to another.
PHOTO OF IC?
The "C" in CMOS stands for complementary, in regard to the "doping" of the two transistors which make up the "totem pole" output.
Again we see our splitter diagram on the left, mimicked on the right by two MOS transistors, one p-channel, the other n-channel (complementary to each other). These MOS transistors act as switches-only one can be closed at a time. Thus CMOS chips consume almost no power when they are not switching. When a CMOS inverter switches, there is a brief time when charge can flow through both transistors. Power consumption in CMOS devices is proportional to switching frequency.
PHOTO OF IC?
The "C" in CMOS stands for complementary, in regard to the "doping" of the two transistors which make up the "totem pole" output.
Again we see our splitter diagram on the left, mimicked on the right by two MOS transistors, one p-channel, the other n-channel (complementary to each other). These MOS transistors act as switches-only one can be closed at a time. Thus CMOS chips consume almost no power when they are not switching. When a CMOS inverter switches, there is a brief time when charge can flow through both transistors. Power consumption in CMOS devices is proportional to switching frequency.
CMOS is a NAND-based family, like TTL. A CMOS 2-input NAND gate is shown below in (a). A switching circuit interpretation is in (b). Notice there are 2 kinds of switches, one SPST which closes in response to HI, and another which opens. Also, no resistors are needed in the CMOS circuit, other than the resistances of the gates themselves.
Otherwise the switching circuit above looks like the EXOR gate designed in §1. Both inputs are HI in the case above, causing OUT to be grounded.
Otherwise the switching circuit above looks like the EXOR gate designed in §1. Both inputs are HI in the case above, causing OUT to be grounded.
Power supply tolerance (=range of acceptable power supply voltage) is much greater in CMOS than TTL. Because of low power consumption and tolerance of power supply voltage, CMOS is favored in consumer electronics powered with batteries, such as digital watches (where, also, low-power liquid crystal displays are favored over LED's). More modern CMOS families, such as ACT or HCT, are designed to operate around a narrower power supply range, such as 2-6 volts.
S2 / 3 / 3 Bipolar - CMOS hybrid
TTL-CMOS interfacing between logic levels was discussed in the previous §. Here we draw your attention to a logic family BiCMOS, which uses CMOS transistors for input, and bipolar (TTL) transistors for output. The result is a hybrid logic family with good packing density, low power consumption, and excellent speed. The CMOS front end results in high input impedance and good noise margin, and high fanout. BiCMOS chips provide an automatic interface from TTL to CMOS, and are comparable to TTL-AS in speed and better with regard to power. A 74BC00 chip consumes 6mA of current when output is LO, and 10 mA when output is HI. It's propagation delay into a 50pF-500W load is 3.8 nsec. A BiCMOS flip flop can operate at up 100 MHz clock rate.
Motorola BiCMOS Logic Data (1990).
S2 / 4 Logic families specialized for speed
TTL chips are generally faster than CMOS gates (but see ACT series), however there are two logic technologies faster than TTL-Emitter-coupled logic (ECL) and gallium arsenide (GaAs). These chips come at considerable cost in power consumption and ease of interface to other logic families. Chips in the TTL AS family, and CMOS HC family are quite fast, consequently the motivation to use ECL parts has dropped in recent years.
S2 / 4 / 1 Emitter-coupled logic (ECL)
ECL technology has been around longer, so let's consider it first. ECL is a non-saturating type of silicon bipolar design. TTL is a saturating bipolar design. Keeping transistors out of saturation decreases propagation delay (and minimizes amount of switching noise generated). The boxed material can start you understanding how a basic ECL inverter works as a "differential amplifier." Instead of switching voltage levels at one output, ECL switches current flow in two arms of the circuit; one byproduct of ECL switching: Both a variable and its complement are available as chip outputs. Within its family, 10K ECL has good fanout. Interface to TTL and CMOS is awkward because of different power supply ranges.
Noise margins, measured in volts, are much smaller in ECL than TTL, but there is some compensation in the fact that ECL circuits are less noisy than TTL. Propagation times for commercial ECL families are close to one nanosecond. Unfortunately ECL chips consume a lot of current, up to 60mA per gate in the 100K family.
ECL gates can be thought of as current mode devices, where current flows through one or another arm of the differential pair, depending on the state of the circuit.The basic ECL inverter design, shown below, starts with a transistor over an emitter resistor, like we've seen in the TTL splitter. The idea will remind you of an analog differential amplifier.
On the right above is shown the emitter-coupling which is the basic building block of ECL; current through either transistor will create a voltage drop across Rem. Let a high IN = 4.4v. If the ratio of Remitter to Rcollector is carefully adjusted, then Remitter limits the total current through the transistor and keeps the transistor out of saturation. Depending on the state of the ECL switch more current will flow through one or the other of the collector resistors. Unconnected ECL inputs float low.
On the right above is shown the emitter-coupling which is the basic building block of ECL; current through either transistor will create a voltage drop across Rem. Let a high IN = 4.4v. If the ratio of Remitter to Rcollector is carefully adjusted, then Remitter limits the total current through the transistor and keeps the transistor out of saturation. Depending on the state of the ECL switch more current will flow through one or the other of the collector resistors. Unconnected ECL inputs float low.
In commercial ECL families (10K is the most popular) the power supply is actually -5.2 volts, connected where ground is above; +5 in the drawing above is at ground. With the power supply on the common emitter resister Rem, the circuit has more immunity to spikes on the power lines, and in fact ECL has much less problem than TTL with switching spikes, since ECL current magnitudes do not change during transitions.
Great care must be taken with the construction of ECL circuits operating near their maximum clock rates; for example, ordinary wires connecting chip outputs and inputs must be less than 10 cm, or be made as terminated transmission lines, to avoid spurious ringing.
Motorola MECL Device Data (1989) &
Motorola MECL System Design Handbook (1983).
These books describe the 10K logic family.
Motorola MECL System Design Handbook (1983).
These books describe the 10K logic family.
S2 / 4 / 2 Gallium Arsenide
Gallium Arsenide (GaAs) chips are not based on silicon. Silicon, like carbon, is in column IV of the periodic table. Gallium is in column III and arsenic in V. Depending on the ratio of Ga to As, a mixture of gallium and arsenide can have a crystal structure with a desired conductivity. GaAs is a semiconductor with higher mobility.* GaAs chips can switch as rapidly as ECL, in the sub-nanosecond range, but consume only ¼ the power. GaAs materials, however, lack a hard insulating oxide comparable to silicon dioxide, so GaAs semiconductors are limited in the gate packing density which can be achieved. *
It would seem that purveyors of a new technology, such as GaAs, would consider implementation in general-purpose "gate arrays" to finesse the problem of manufacturing the hundreds of standard chips needed to compete with established families of TTL and CMOS. GaAs is less evolved as a logic family than ECL, in fact there is no standard GaAs family. See offerings by Gazelle Inc. and Vitesse Corp. Gazelle produces a 22V10 PAL with 5.5 ns tpd. Besides digital, GaAs transistors have numerous applications in high speed analog design.
(3) Mun, Joseph, (ed) GaAs Integrated Circuits-Design & Technology, Macmillan Publishing, 1988 TK7874 / G33 See chapter 3, "Digital integrated circuit technologies."
S2 / 5 Packing density
All other things being equal, shorter connections will make for a faster circuit. And shorter connections will have less loading capacitance. The shortest connections are made directly on the integrated circuit chip itself. Such IC connections must be made by photolithography; they are more reliable than hand or machine connected wrapped wires or printed circuit board routing. As a result, the number of gates per IC, the packing density, can be an important factor in selecting a logic family for a job. In the regard of packing density, CMOS is the leading technology. CMOS memory chips with 64 million transistors have been fabricated.
S2 / 6 Chart comparing logic families
The following chart compares, qualitatively, state of the art TTL and CMOS with ECL 100K and GaAs logic, in 7 different categories.
Not so fast.
Not so fast.
Input: A matter of noise margin. In a densely packed integrated circuit, with thin interconnection wires (1-3 mm), some gates may see power supply voltages and signals which have been contaminated by noise. How well the gates reject the noise can be an important consideration, but not as important as speed, power consumption and packing density in the scale of things. Fortunately, as we know, digital circuits can be quite forgiving with regard to variations in LOW and HIGH signal ranges. This, in fact, is one reason digital IC's have progressed to much denser packing than analog IC's. Switching speed, our primary digital IC quality, is perversely related to noise produced in chips and systems. The faster the transition from one state to the other by a switch, the more current transients generated by the switch and throw noise (either as local E-M radiation, or a power supply glitches) into the neighboring system. In the special category of memory IC's, problems can arise with regard to the altering of memory contents by EM radiation, and from radioactive decay in the packaging material (thorium contamination of ceramics).
Evolutionary "forest" of digital logic and other intelligence:
S2 / 7 Logic families vs programmable logic devices
The invention of the microprocessor in the 1970's started an era in which general-purpose large-scale integrated circuits could be called upon to perform many logic tasks (central processing in a computer, for example) formerly done by circuit board assemblies of chips from particular logic families. Small- and medium-scale integrated circuits in the form of gates and flip flops from logic families then become "glue" in the service of the large chips, providing specialized interface capabilities. In the 1990's "random logic" (SSI and MSI gates from logic families) will be more and more replaced with programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). A designer will no longer leaf through a data book looking for a chip which does some of what he or she wants; rather the designer will layout and simulate with software his or her ideas for a design, then program a general-purpose chip to implement those those needs. In both cases, whether with gates and flip flops from a logic family or with a FPGA, chips are the final product, but with FPGAs it may be only one chip, and that chip may have as many as 176 pins.
The question to answer: What logic families do FPGAs and other PLD's belong to? The short answer is CMOS. CMOS is the preferred technology because of the ease with which many transistors can be placed on one IC, and because of the low power consumption of the resulting configuration. Modern CMOS fabrication results in speeds which approach advanced TTL. Except in cases where the fastest speed is an essential requirement of a design, CMOS gate arrays will be the dominant technology for random logic hardware in the next decade.
Especially through the 1970's the 7400 series of TTL gates, at small and medium scale integration were used for much of digital logic design, especially the CPU's of high speed computers. However, starting with memory chips, and later progressing into monolithic microprocessors, MOS fabrication took increasing market share. Especially in low power CMOS form the greater packing density of MOS technology assured it an improving "survival" rate. In some cases it's possible to combine both technologies in a single chip: BiMOS as it's called. Now-a-days most IC's can be accommodated with MOS technology, except in high-speed requirements, where bipolar ECL, and now GaAs, remain necessary. Supercomputers maintain their high speed by short interconnects as well as by fast chips. Random logic, picked by an engineer to optimize a particular design, is now being replaced by standard gate arrays, which have more in common with systematic memory organizations than with Karnaugh-map & excitation map minimized designs.
New Technology. Carbon is in the same column of the periodic table as silicon. Integrated circuits are not based on carbon because carbon is not easily turned into crystalline form. Carbon in crystalline form is called diamond. Recent progress in synthesizing diamond may make carbon a realistic atom on which to base future forms of integrated circuit (Science 252: page 375, April 19, 1991). Diamond IC's would be faster and have better heat characteristics.
And see Nature 350: 561-62, April 18, 1991, "Dawn of the diamond chip," by L.M. Brown. Review of work from Japan on the development of diamond p-n junction diode. Diamond has better thermal conductivity than silicon; diamond chips might be able to operate at 1000°C. Perhaps the elusive blue LED could be constructed on diamond substrate.
October 1992 Scientific American page 84, "Diamond Film Semiconductors," by M. W. Geis & J.C. Angus. Best thermal conductivity of any material at room temperature. Diamond semiconductors would operate at high speed, high temperature. Diamond is a metastable state of carbon.
S2 / 8 Summary
- Propagation delay is the time between presentation of input and change of output to a new logic level. For modern solid state logic gates propagation delays are in the range of nanoseconds.
- If it has different kinds of inputs, such as data, select, enable, etc, one logic chip will need several propagation delays to specify it, depending on which kind of input is tested versus output.
- IC chips consume power in either static or dynamic modes. Dynamic power dissipation is proportional to rate of switching and is important in CMOS chips.
- IC Power consumption is generally correlated with propagation delay-all other things being equal, the shorter the propagation delay, the more energy used by the switch.
- A delay-power factor allows for comparison between logic gates; the lower the DP factor, the better the gate's performance.
- Power consumption results in heat production, which can degrade chip performance and, if it exceeds limits, can irreversibly damage the chip. Excess heat may precipitate another cost-cooling of a circuit. In the future, solid state circuits based on synthetic diamond may prove more heat resistant than any current logic family.
- High speed switching can result in generation of large current transients, which sneak around the power supply wires, invading other chips, like gremlins.
- Transistor-transistor logic (TTL) is a bipolar super-family with many sub-families, coded 74FamXXX. The most important TTL subfamilies are the ones which incorporate Schottky diodes to increase speed without excess increase in power consumed.
- The Complementary Metal-Oxide-Semiconductor (CMOS) super-family has several sub-families compatible with 7400 series pinouts. Compared to TTL, CMOS chips dissipate less power, are more tolerant of power supply voltage variations, and can pack more transistors per chip. CMOS technology is applied to microprocessors, memory and FPGAs.
- Emitter coupled logic and Gallium Arsenide technology are two of the fastest forms of electronic logic; GaAs gates in particular have sub-nanosecond propagation delays. ECL and GaAs gates consume much more power than TTL or CMOS gates, and can't be fabricated to the high level of integration that TTL or CMOS can.
- A comparison of logic families suggests that a designer must make choices on the basis of power dissipation, propagation delay, $$ cost, packing density, fanout, and noise margin
Static precautions
Many ICs are static sensitive and can be damaged when you touch them because your body may have become charged with static electricity, from your clothes for example. Static sensitive ICs will be supplied in antistatic packaging with a warning label and they should be left in this packaging until you are ready to use them.
It is usually adequate to earth your hands by touching a metal water pipe or window frame before handling the IC but for the more sensitive (and expensive!) ICs special equipment is available, including earthed wrist straps and earthed work surfaces. You can make an earthed work surface with a sheet of aluminium kitchen foil and using a crocodile clip to connect the foil to a metal water pipe or window frame with a 10k
resistor in series
It is usually adequate to earth your hands by touching a metal water pipe or window frame before handling the IC but for the more sensitive (and expensive!) ICs special equipment is available, including earthed wrist straps and earthed work surfaces. You can make an earthed work surface with a sheet of aluminium kitchen foil and using a crocodile clip to connect the foil to a metal water pipe or window frame with a 10k
resistor in seriesSinking and sourcing current
IC outputs are often said to 'sink' or 'source' current. The terms refer to the direction of the current at the IC's output.If the IC is sinking current it is flowing into the output. This means that a device connected between the positive supply (+Vs) and the IC output will be switched on when the output is low (0V).
If the IC is sourcing current it is flowing out of the output. This means that a device connected between the IC output and the negative supply (0V) will be switched on when the output is high (+Vs).
It is possible to connect two devices to an IC output so that one is on when the output is low and the other is on when the output is high.
The maximum sinking and sourcing currents for an IC output are usually the same but there are some exceptions, for example 74LS TTL logic ICs can sink up to 16mA but only source 2mA.
Using diodes to combine outputs
The outputs of ICs must never be directly connected together. However, diodes can be used to combine two or more digital (high/low) outputs from an IC such as a counter. This can be a useful way of producing simple logic functions without using logic gates!
The diagram shows two ways of combining outputs using diodes. The diodes must be capable of passing the output current. 1N4148 signal diodes are suitable for low current devices such as LEDs.
For example the outputs Q0 - Q9 of a 4017 1-of-10 counter go high in turn. Using diodes to combine the 2nd (Q1) and 4th (Q3) outputs as shown in the bottom diagram will make the LED flash twice followed by a longer gap. The diodes are performing the function of an OR gate.
The diagram shows two ways of combining outputs using diodes. The diodes must be capable of passing the output current. 1N4148 signal diodes are suitable for low current devices such as LEDs.
For example the outputs Q0 - Q9 of a 4017 1-of-10 counter go high in turn. Using diodes to combine the 2nd (Q1) and 4th (Q3) outputs as shown in the bottom diagram will make the LED flash twice followed by a longer gap. The diodes are performing the function of an OR gate.
Example projects:
Logic ICs
Logic ICs process digital signals and there are many devices, including logic gates, flip-flops, shift registers, counters and display drivers.
Logic ICs can be split into two groups: the 4000 series, and the 74 series which consists of various families such as the 74HC, 74HCT and 74LS.
For most new projects the 74HC family is the best choice. The tables show the supply voltage and maximum output current for each family. The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.
Logic IC inputs have high impedances and unused inputs must be connected to 0V or +Vs to avoid erratic behaviour due to inputs switching state in response to stray electrical noise. 74LS ICs are unusual because their inputs 'float' high when unconnected.
The number of logic IC inputs which can be driven by one output of the same family is called the fan out. Usually 50 (10 for 74LS), it is unlikely to matter in simple circuits.
For more details of the logic IC families, including pin arrangements for many ICs, please see these pages:
Logic ICs can be split into two groups: the 4000 series, and the 74 series which consists of various families such as the 74HC, 74HCT and 74LS.
For most new projects the 74HC family is the best choice. The tables show the supply voltage and maximum output current for each family. The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.
Logic IC inputs have high impedances and unused inputs must be connected to 0V or +Vs to avoid erratic behaviour due to inputs switching state in response to stray electrical noise. 74LS ICs are unusual because their inputs 'float' high when unconnected.
The number of logic IC inputs which can be driven by one output of the same family is called the fan out. Usually 50 (10 for 74LS), it is unlikely to matter in simple circuits.
For more details of the logic IC families, including pin arrangements for many ICs, please see these pages:
- 4000 series
- 74 series (74HC, 74HCT & 74LS)
| Logic IC family | Supply voltage |
| 4000 series | 3 to 15V |
| 74HC | 2 to 6V |
| 74HCT | 5V ±0.5V |
| 74LS | 5V ±0.25V |
| Logic IC family | Maximum output current |
| 4000 series | about 5mA (10mA with 9V supply) |
| 74HC | about 20mA |
| 74HCT | about 20mA |
| 74LS | sink 16mA source 2mA |
| To switch larger currents use a transistor. | |
4000 series ICs | 74 series ICs
Mixing Logic Families
It is best to build a circuit using just one logic family, but if necessary the different families may be mixed providing the power supply is suitable for all of them. For example mixing 4000 and 74HC requires the power supply to be in the range 3 to 6V. A circuit which includes 74LS or 74HCT ICs must have a 5V supply.
A 74LS output cannot reliably drive a 4000 or 74HC input unless a 'pull-up' resistor of 2.2k is connected between the +5V supply and the input to correct the slightly different logic voltage ranges used.
Note that a 4000 series output can drive only one 74LS input.
A 74LS output cannot reliably drive a 4000 or 74HC input unless a 'pull-up' resistor of 2.2k
is connected between the +5V supply and the input to correct the slightly different logic voltage ranges used.Note that a 4000 series output can drive only one 74LS input.
Driving 4000 or 74HC inputs from a74LS output using a pull-up resistor.
PIC microcontrollers
A PIC is a Programmable Integrated Circuit microcontroller, a 'computer-on-a-chip'. They have a processor and memory to run a program responding to inputs and controlling outputs, so they can easily achieve complex functions which would require several conventional ICs.Programming a PIC microcontroller may seem daunting to a beginner but there are a number of systems designed to make this easy. The PICAXE system is an excellent example because it uses a standard computer to program (and re-program) the PICs; no specialist equipment is required other than a low-cost download lead. Programs can be written in a simple version of BASIC or using a flowchart. The PICAXE programming software and extensive documentation is available to download free of charge, making the system ideal for education and users at home. For further information
If you think PICs are not for you because you have never written a computer program, please look at the PICAXE system. It is very easy to get started using a few simple BASIC commands and there are a number of projects available as kits which are ideal for beginners.
============ MA THE 40XX AND 74XX LOR MATIC FAMILY IC ============
https://www.onsemi.com/pub/Collateral/MC14093B-D.PDF (CD4093 internal gates)
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