Electronics Prognostics in reference to survival of electronic equipment in the forecast for the coming age of electronic intelligence systems sustainable AMNIMARJESLOW AL DO FOUR DO AL ONE LJBUSAF thankyume

          


             

     
                                                                         X  .  I 
     Reviews direct meaning and Differences Between Diagnosis and Prognosis in electronic equipment  



we often hear the term diagnosis and prognosis more often in their treatment is not limited to that alone. Diagnosis refers to identifying the nature or cause of certain phenomena and prognosis refers to future conditions. 


Diagnosis
Diagnosis can be defined as identifying the nature or cause of certain phenomena. It determines the relationship between cause and effect. In medicine, physicians arrive at a diagnosis by carefully reviewing the history, examination findings, and the results of the investigation. Clinical interview involves composing the list and narrowed them down. For example, if a patient presents with knee joint pain, your doctor may think about the trauma, arthritis, or referred pain. After a careful history and examination, the doctor removes the less likely the cause of the list. At this stage, the doctor has a small list of diagnostic possibilities. This is called differential diagnosis. Investigations have to arrive at a diagnosis or to confirm the clinical suspicion.
Computer technician uses various models to arrive at a diagnosis of technical problems. Example: Bayesian networks, foundations Hick am  and foundation  Sutton. Is a psychological methods and technology solutions are used by professionals, to arrive at a diagnosis. 



Prognosis
Prognosis refers to future conditions. It describes the possible condition to be resolved. In the treatment, the prognosis can be good or bad. Prognosis is not a destination but measurement of subjective comments by previous cases.
Good prognosis means that the patient is very likely to recover, and the threat to life is less. Bad prognosis means that the chances of survival are poor.
Prognosis not give an idea of ​​the duration. In cancer, the patient may suffer for a long time or it could die the next day.
In both cases, the prognosis is poor. Minor injuries, a common cold have an excellent prognosis. In medicine, a clear diagnosis is required to give a prognosis. In difficult to diagnose cases of evil, doctors struggled to answer tough questions such as "How long has he?"reviews electronics prognosis
we are an electronics engineer who has a role as a doctor in the system prognosis electronics that detect electronic equipment may survive how long eg  satellites in outer space, space shuttle, Robo ( Ringing on Boat ) future with recommendations of data for us to explore the space that has no air ( oxygen), so here's prognosis electronics is the ability to measure and verify the age of all the equipment the equipment produced by electronics engineering .


What is the difference between the Diagnosis and Prognosis?

• Diagnosis explain the reason for the symptoms.

• Prognosis describes how likely it is to go. 


so the conclusion prognosis is a prediction of events that will occur, especially those related to the disease or healing after surgery, when in the field of electronics is the prediction of events that will occur in electronic equipment such as would occur may not function or slowing the work process of electronic equipment such as well as how how to handle the equipments of electronic equipment that can function in their function under normal circumstances as well as optimal. 


so the prognosis, the forecast medical and examination results and diagnoses based on theories or research on the disease (if humans or animals and plants) or in the electronic equipment that disrupt the work of electronic equipment such as satellites, robo ( Ringing on Boat ) or TV, radio, radar and other etc. are concerned.

Chances are:
                 a) Tend good (ad dubia bonam)
                 b) Tend to deteriorate (ad dubia night) 

The next step is a step prognosis for estimating (measuring), estimate whether the difficulty / the case may be helped or not. Prognosis is an approximate measure that can be applied or the possibility of assistance. Prognosis is an early conclusion to a case to provide therapy or step programmatically. 


                                                                    X  .  II  
 

                                                        Electronics Prognostics  

Introduction

Post mortem analysis is a process that identifies the failure modes involved with electronic component failure through mechanical, electrical and chemical tools. Systematic identification is useful in determining the underlying physical failure mechanisms, which can ultimately lead to pinpointing the failure's root cause.

Techniques

The techniques involved with post mortem analysis span a broad application of tools and processes which can typically be accomplished within two failure analysis categories: non-destructive and destructive.

Non-Destructive Techniques
The non-destructive post-mortem technique involves non-altering means for analyzing the sample. No part of the sample undergoes chemical, electrical or mechanical related stress. Typically, non-destructive techniques involve quick external visual inspections, which can range from sophisticated microscopy methods to x-ray radiography analyses. Examples of non-destructive methods include the following:

External Visual Inspections

Electrical Characterizations

Optical Microscopy

X-ray Radiography

Curve Tracing

Destructive Techniques
Destructive techniques cause permanent and usually irreversible changes to the sample. This can be done by electrical, chemical or mechanical means, or a combination thereof. Typically, destructive techniques should proceed after non-destructive methods have been exhausted, because the outcome of this test is intended to cause physical alteration to the sample. The various applications of destructive failure analysis methods include:

Sectioning

Decapsulation

Scanning Electron Microscope (SEM)

Chemical Analysis

Heat Spot Detection  

CASE STUDY - Insulated Gate Bipolar Transistor (IGBTS)

IGBT electronic components are important to investigate since they are quickly becoming the device of choice in electronic power engineering. Their hybrid structure, consisting of a BJT and MOSFET, makes them an attractive choice for designs which call for fast switching speed with minimal power consumption. Unfortunately, these components are not without their faults, and investigating these faults involves a broad range of tools and applications. Two non-destructive methods are explored below.
BACKGROUND
Several IGBTs that had undergone stress tests were examined. Based on the responses during tests, the parts were considered to have experienced only mild to medium damage. Electrical parameters of the two parts were measured and compared with the datasheet limits. Then, the parts were examined via X-Ray inspection using facilities in collaboration with CALCE (UMD).
X-RAY INSPECTION
The X-ray inspection revealed damage that may have occurred at the die-attach of the parts. The X-ray image of an un-stressed part is shown for comparison. The die attach at the stressed part shows possible voids. Such voids are likely to increase die temperature of the parts.

Prognostics for Electronics

This project investigates aging characteristics of power semiconductor components as well as development of algorithms for remaining life estimation. In contrast to the common and mature reliability work done in the semiconductor industry, this work focuses on condition-based health management. That is, determination of the presence of abnormal conditions and estimation of remaining life depending on anticipated future use. Such information can be vital in improving the safety of operations and can contribute significantly in improving mission success rate as well as reducing cost of unscheduled maintenance. To that end, we investigate the basic fault mechanisms of power semiconductors that are commonly found in aerospace applications. Aging platforms are being built and models capturing physics-of-failure are being designed in conjunction with algorithms for end-of-life prediction.

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Motivation

Fault diagnosis has traditionally been employed to some safety-critical mechanical systems or to those for which downtime constitutes considerable financial loss. Typically, sensors monitor environmental and loading conditions in the application environment. Algorithms are then designed to extract information from the sensor readings, and compare them against a baseline to determine whether abnormal conditions exist and, if yes, what the root cause might be. While this technology has been matured to some degree for mechanical (and also structural) systems, what has been ignored until recently is that most of today's complex systems contain significant amount of electronics. Indeed, there is apriori reliability evidence that electronics may fail earlier than mechanical components.
In the aerospace domain, flight and ground crews require health state awareness and prediction technologies across all systems (including structures, propulsion, and various subsystems) that can accurately diagnose faults, anticipate failures, and predict the remaining life. This includes those from avionics. Indeed, electronic components have an increasingly critical role in on-board, autonomous functions for vehicle controls, communications, navigation, radar systems, etc. Future aircraft systems, such as the more electric aircraft or the Next Generation Air Transportation Systems (NGATS) will certainly rely on more electric and electronic components. The assumption of new functionality will also increase the number of electronics faults with perhaps unanticipated fault modes. In addition, the move toward lead-free electronics and Micro-Electro-Mechanical Systems (MEMS) will further result in unknown behavior. To improve aircraft reliability, assure in-flight performance, and reduce maintenance costs, it is therefore imperative to provide system health awareness for digital electronics. To that end, an understanding of the behavior of deteriorated components is needed as well as the capability to anticipate failures and predict the remaining life of embedded electronics.
The development and advancement of this capability is also relevant to multiple Exploration Systems Mission Directorate (ESMD) vehicles, including the Orion, Ares, and future vehicles such as Lunar Surface Access Module (LSAM). In addition, there is relevance to long-endurance robotic space missions from ESMD and SMD. 

Understanding of Degradation Mechanisms

Generally, an understanding of intrinsic and extrinsic degradation mechanisms of component level devices is crucial for the adoption and application of health management to systems. Within the field of electronics, knowledge of semiconductor degradation under various system and environmental scenarios may be coupled with prognostic algorithms to predict future state and time–to–failure of semiconductor components.
The existence of measurable extrinsic degradation precursors, pertaining to device packaging, has been well established in literature for power transistor devices. In recent literature intrinsic degradation precursors, related to the physical properties of the semiconductor, have also been observed. However, it is not widely known how degradation mechanisms propagate as a function of environmental conditions and various stressors. The attainment of such knowledge is critical for advancements in the field of power electronics health management and prognostics. Therefore, the ability to perform large scale experiments on semiconductor devices for characterization of degradation precursors under various scenarios is of great interest. Additionally, the first phase of system implementation and its initial application to Insulated Gate Bipolar Transistors (IGBTs) in a thermal overstress scenario is presented.

Approach

To advance the field of electronics prognostics, the study of transistor fault modes and their precursors is essential. The objective is to focus on a platform for the aging, characterization, and scenario simulation of gate controlled power transistors. The platform supports thermal cycling, dielectric over-voltage, acute/chronic thermal stress, current overstress and application specific scenario simulation. In addition, the platform supports in-situ transistor state monitoring, including measurements of the steady-state voltages and currents, measurements of electrical transient response, measurement of thermal transients, and extrapolated semiconductor impedances, all conducted at varying gate and drain voltage levels. The aging and characterization platform consists of an acquisition and aging hardware system, an agile software architecture for experiment control and a collection of industry developed test equipment.

Accelerated Aging Methods

Thermal stress and electrical stress are the most common aging methodologies. Thermal cycling and chronic temperature overstress are prevalent thermal stress methods, with thermal cycling among the most prevalent accelerated aging methodology in electronics. Thermal cycling subjects devices to rapid changes in temperature differentials causing thermal expansion and contraction. Die solder degradation and wire lift are associated strongly with this aging method. Previous experiments on Metal-Oxide-Semiconductor FETs (MOSFETs) cycled 7000 times from -50°C to 100°C resulted in void formation in over 30% of the die solder attachment. Similar results were demonstrated in IGBTs under power cycling with wire lift also occurring. It should be noted that this effect is solder dependent, with lead-free packages showing better resistance to solder degradation. Thermal overstress, another prevalent method, subjects devices to high temperatures for extended periods of time. TDDB is accelerated under high temperatures and transistors have exhibited temperature dependant lifetimes accelerated by this mechanism. IGBTs aged with self heating have shown changes in current ringing characteristics during switching.
Electrical overstress can be induced though transient and steady-state methods. Transient methods include electro static discharge (ESD), inductive switching and electromagnetic pulses. ESD is a leading cause of gate oxide failure and hard switching of inductive loads, causes voltage spikes which can cause significant damage to drain-source junctions. One can distinguish between thermally induced failure mechanisms (contact metal burnout, fused metallization), and electric field induced damage. Steady-state methods include chronic over-voltage and over-current. Applying high gate voltages, setting gate voltage (V_g) to maximize drain current, and applying current overstress across the drain have been shown to induce hot carrier and TBBD. Fault precursors that could be monitored, amongst others, appear as collector-emitter leakage, gate leakage, changes in gm and shifts in V_gth.
System Requirements:
This section describes the design and implementation of a system capable of performing accelerated aging tests, application simulations and device characterization on gate controlled power transistors to induce and analyze fault precursors. The proposed system should have the ability to act as test bed for the validation of prognostic algorithms for power transistors. System requirements relevant to these goals are:

• Accommodate gate controlled power transistors by operating on standard and commercially available MOSFETs and IGBTs with currents capabilities ranging from 1A to 50A in typical 3 pin packages.
• Accelerate aging of transistors, wherein electrical signals and environments can be carefully controlled to laboratory standards.
• Simulate various application specific scenarios, including scenarios with extreme environmental conditions.
• Measure and record electrical signals and environmental properties associated with test scenarios. In addition, the system must perform tests to extract transistors physical and electrical characteristics.
• Have the ability to interface with prognostic algorithms such that real-time prognostics can be achieved.
• Incorporate flexibility such that new instrumentation or software modules can be added with minimal effort. The system should be scalable, allowing multiple transistors to be tested in parallel. The software must be agile, such that new requirements can be incorporated without significant software redesign.
• Perform aging and characterization tasks autonomously. User intervention should only be required to design, configure or initiate a test sequence.

Design considerations
Transistor Gate Hardware - Arbitrary signal generation is required over the full voltage range of a transistor gate for the support of robust scenario simulation and characterization. A review of industry datasheets yields rise and fall times on the order of 10ns and 50ns, for the specified class of MOSFETS and IGBTs. Gate voltages are limited to a 20V maximum for both transistors. A driver that exceeds this maximum would be useful for hot carrier injection and TDDB aging scenarios. Slew rates in excess of 2V/ns are desired for fast large signal swings. Gate capacitances for specified transistors are typically in the range of 500pF for MOSFETs and 6nF for IGBTs, requiring a powerful gate driver. The necessity for arbitrary signal generation at the transistor gate suggests the use of a linear amplifier. A driver bandwidth in excess of 100MHz is desired. Additional equipment with higher performance or special functionality may need access to the transistor gate. Therefore, the gate circuit should incorporate a switching mechanism between various instruments. A switching network for the electrical isolation of the gate should also be implemented where leakage or high voltages may cause problems.
Load and Power Supply Hardware - It is desirable to accommodate load currents from 10A up to 100A. Contacts and Printed Circuit Board (PCB) components must be rated for high amperages. Power supplies voltages should be programmable to accommodate dynamic scenarios. Power conditioning is desired to reduce interference from power supply feedback circuits or power cable inductance. Dynamic loads are desirable for the emulation of rich system scenarios.
Hardware Electrical Signal Acquisition - The transient response of voltage and current signals corresponding to the gate-emitter and the collector-emitter nodes should be measured in-situ. Transient acquisition rates greater than 1ns are desirable and bandwidths in excess of 300MHz are required to measure rise and fall times. PCB design must take transients into consideration. Overlap between collector and emitter traces should be minimized to reduce parasitic capacitance that may change transient characteristics. Traces should be kept very short or be impedance matched to prevent signal reflection. If possible, instrumentation amplifiers should be used for isolation and common mode rejection. Low-pass filtered transistor signals should also be measured. These averaged signals are especially important for SMPS (Switch Mode Power Supply) applications. Power management ICs (Integrated Circuits) in SMPS already implements voltage monitors, making them an ideal candidate for future prognostic implementations.
Hardware Thermal Environment - Controlling thermal environment is important for transistor characterization as their characteristics are heavily temperature dependant. Datasheets reveal Vgth shifts on the order of -10mV/°C. Collector-emitter resistances will often change by an order of magnitude over a 100°C differential. Such shifts must not be attributed to changes in the intrinsic characteristics of the transistor. In addition, aging and simulation scenarios involve extreme environmental conditions. The system should allow temperatures ranging from far below 0°C to above 300°C, where IGBTs have shown short-term operability. Internal junction temperature measurements, often measured using Vgth, can be problematic as hot carrier effect also acts on Vgth. Special effort should be taken to measure silicon die, package epoxy and package heat sink temperatures using thermal methods, in order to enable accurate temperature control and thermal impedance degradation measurements.
Software Control and Data Acquisition-The chosen software development environment must support communication with multiple hardware devices, act as an in-the-loop feedback controller, and save gigabytes of data collected over long test runs. The test software must perform a multitude of different experiments related to scenario generation and transistor characteristics. It should interact easily with the user and display results in real-time.
Software Architecture - The software framework controlling the system should enable a dynamic and scalable development environment. Scientific software development is usually iterative, where results dictate new and novel experiments. Equipment upgrades will require system adaptation. A thorough consideration of software engineering principles is crucial to the development of a successful software package.

Problem Description

The assumption of new functionality of electronics will increase the number of faults with perhaps unanticipated fault modes. In addition,the move toward lead-free electronics and MEMS will further result in unknown behavior. It is therefore necessary to gain an understanding of the behavior of deteriorated components. Different environmental and operational conditions from conditions typically seen in ground-based applications may impact the deterioration in different ways. Anecdotal information reports that, for example, the mounting direction of circuit boards has an impact on the frequency of intermittent faults since they are flexing in a particular way when subject to accelerations during take-off, causing temporary disconnects. Some of the conditions, besides high acceleration, that may impact proper operation includes operation in extreme temperatures and temperature cycling, vibrations, humidity, power cycling, radiation, and a combination thereof.
                                                   
Figure 1: IGBT with extreme damage

Common Extrinsic IGBT Faults

Extrinsic faults are faults that are associated with the external components of the die such as packaging, wires and solder.
Table 1: Extrinsic IGBT faults

Fault	Cause	Effect
Wire Lift	-CTE mismatching -Bond looping and lagging -Dendrite growth -Wire sweep -Bonding pressure -Metal electro-migration	-Increase in wire resistances -Wire detaches from package / die causing an open circuit -Short circuit between bonds due to metal migration or dendrite growth
Die/Package Solder Degradation	-CTE mismatch between die and package -Thermal cycling of solder crystalline structure	-Voids formed in die/package interface -Increase in internal temperature -Thermal degradation

Possible Prognostic Signatures for Wire Lift

Degradation Wire Lift - Degradation wire lift would likely be seen as an increase in resistance across the Gate or Collector/Emitter junction.

An increase in resistance across the gate is directly measurable by holding a constant Vce (Collector/emitter voltage), Vge (Gate emitter voltage) and measuring the Ice (Collector/Emitter current). Internal temperature of the silicon die has a significant effect on the internal resistance of the collector/emitter channel, thus a correction must be applied depending on the internal temperature of the IGBT. This internal temperature must be explicitly calculated, as a measurement made using the package temperature does not account for solder/die bond degradation. Measuring an increase in gate wire resistance proves more difficult, as the gate has complex impedance.

Common Intrinsic IGBT Faults

Intrinsic faults are the faults that are inherent to the operation of the device. These faults independent of the device packing and usually have a cause rooted in the semiconductor materials or underlying physics of the device.
Table 2: Intrinsic IGBT Faults

Fault	Cause	Effect	Physics
Thermal Runaway	-Overheating of the IGBT die	-Short circuit -Smoke and fire	-Negative resistance/temperature coefficient
Latch Up	-Heat degraded silicon -Lowering of parasitic SCR holding voltage	-IGBT stuck in on-state	-Parasitic NPN BJT forms a SCR with PNP BJT
Time Dependent Dielectric Gate Breakdown/ Acute gate Breakdown	-Chronical electrical overstress -Thermal cycles -Transient voltage spikes -Manufacturing defects	-Decrease in gate speed -Eventual loss of gate control -Increase in leakage current -Change in Vg threshold	-Doping concentration, work function, gate oxide capacitance
Collector/emitter degradation	-Electrostatic discharge -Electrical overstress -Snappy diodes -Contact migration -Thermal degradation	-Increase in R-on -Decrease R-off -Slow I-rise/fall	-Dielectric breakdown of depletion region -Doped silicon gains energy above activation energy
Piping/Contact Migration	-Local hot spots	-Increase in ice leakage current	-Defects in depletion region (change in doping) -Metal/Si alloy from heat

     

     

   Figure 1: Overview of the electrical system.

Test Hardware Overview

Implementation

System Implementation has been broken into several stages to manage project complexity. The system implementation consists of a set of commercially available instrumentation attached to a custom built hardware system under the control of an agile software framework developed in LabVIEW. 
 

Commercial Instrumentation

The industrial hardware consists of a 300MHz Agilent DSO5034A oscilloscope with a 1ns sample rate and 1Mpts memory for large transient acquisition, a 20 MHz Agilent 33220A function generator for gate signal control, a National Instruments PCI-6229 data acquisition card with a SCC-68 breakout containing three SCC-TC02 thermocouple measurement modules and one SCC-RTD01 resistance temperature detector, a DCS2050A analog programmable power supply capable of sourcing 20V and 50A, three thermocouple modules, a Raytek RACI3A infrared sensor, a Tenney T5STR environmental chamber capable of temperature, humidity and pressure control, and a computer running LabVIEW and Matlab.

Transistor Test Board

Custom hardware was developed to compliment the commercial instrumentation and serve as the physical test bed for the transistor under test. This hardware includes a primary test board with a built in 200KHz current sensor with a 100A maximum current, an infrared temperature sensor port, BNC transient output ports connected to the DSO5024A oscilloscope, and a bank of 30Hz low-pass filtered output ports connected to the PCI-6229 data acquisition card. An onboard gate driver switching network allows for the in-situ swapping of two separate gate signal sources. A gate isolation switching network is also implemented to remove unnecessary instrumentation when performing current leakage measurements or tests involving high voltage.

Power conditioner and Load Board

A power conditioner and load board was also constructed. It includes a power conditioning stage with three parallel capacitors with staggered capacitance values of 120mF, 4700uF and 47uF. This filtering system removes cable inductance and power supply interference from most transient measurements. The board also provides a two port swappable load network, allowing three parallel loads across node 1 and two parallel loads across node 2. A freewheeling diode port is also provided. Board voltages are low pass filtered and acquired by the PCI-6229.

 

Gate Driver Board 

Figure 2: Schematic for the linear gate driver with only one of three capacitively coupled operational amplifiers displayed.

The gate driver board consists of four parallel LM7171 linear voltage feedback operational amplifiers (op-amps) operating in a non-inverting configuration with input coupled to an Agilent 33220A waveform generator. The gate driver board has an approximate bandwidth of 100MHz, rail to rail voltages from -2V to 23V and can achieve slew rates of 0.5V/ns into a 50Ω load. The design of the driver, shown in Figure 2, consists of a single op-amp directly connected to the driver board output for DC operation and three additional op-amps capacitively coupled to the driver board output to assist in driving the largely capacitive loads associated with power transistor gates. The capacitive coupling prevents damage to op-amps in the event of gain mismatch during steady-state operation. The driver board additionally contains adjustable feedback resistors used in gain calibration to ensure stable operation.
 

Figure 3: Large signal step response of the gate driver into the IGBT gate.
Figure 3 show a 23V step through a 50Ω resistor across the gate of an IGBT. Rise time is 40ns. Figure 4 shows an impedance test of an IGBT gate. A 0.25V RMS sine wave is coupled with a 5V DC bias. Voltage is measured with an ac coupled oscilloscope across a 50Ω resistor connected in series with the gate.

  
Figure 4: Small Signal response of the IGBT gate used for impedance characterization. 

Thermal Test System

A custom thermal control unit is also under development to attach thermocouples to fixed positions on the transistor package and utilize a Peltier unit capable of 60°C temperature swings in both negative and positive directions for use in rapid thermal cycling. The Peltier unit is driven by a 15A linear amplifier and attached to a large heat sink for that acts as a reservoir for heat dissipation. An infrared sensor is also included for applications requiring contactless measurements, though infrared sensors have exhibited large temperature errors in our applications due to emissivity and beam localization considerations.

 

Results

Preliminary thermal overstress tests were conducted on IGBTs during system development. An International Rectifier IRG4BC30KD IGBT with a 600V/15A current rating in a TO220 package was attached to the transistor test board with no external heatsink. The collector-emitter junction was connected in series with a load power supply and a 0.2Ω load resistor. A 50Ω resistor was placed between the gate driver and the IGBT gate for current measurement. A thermocouple was attached to the IGBT case for temperature measurement. The gate signal was chosen to be a Pulse Width Modulated (PWM) signal with amplitude of 10V, a frequency of 10 KHz and a duty cycle of 40%, similar to a slow SMPS. A hysteresis temperature controller with set points of 329°C and 330°C was connected to the system, switching the gate voltage for its control mechanism. The load power supply voltage was increased from 0V to 4V over the course of several minutes until the heat sink temperature reached 330°C and the temperature controller began cycling. An additional temperature threshold controller, with a set point of 340°C, was programmed to turn off the load power supply and end the experiment in the event of thermal runaway and latching failures. IGBTs tested with this process were found to fail early in the test, within the first several minutes, or survived 1 to 4 hours before loss of gate control and thermal runaway was observed.
Figure 1: Latch up failure of an IGBT during thermal overstress.
Figure 1 shows the averaged collector-emitter current during a failure. The average ON-state current increases from approximately 4A to 10A indicating a transition from a 40% PWM duty cycle to a latched ON-state, resulting from a loss of gate control. This behavior may be attributed to the temperature-stimulated parasitic Silicon Control Rectifier (SCR) found within the IGBT. The experiment was ended quickly after the failure and the IGBT was found to be functional when returned to room temperature of 24°C. Characteristics of the degraded IGBT are currently being examined.
Both steady state and transient switching signals recorded during the test were analyzed. Steady-state voltages and currents showed minimal change throughout the test. Transient gate voltage and current also remained constant. Changes to collector-emitter voltage transient characteristics during turn-ON were also minimal. The collector-emitter current characteristics were not collected during this stage of development. 

 

Figure 2: a) A voltage transient is generated across the collector-emitter junction. This peak decreases as the device degrades. b) A close-up of the transient peak.

A strong degradation indicator was observed when viewing the collector-emitter voltage turn-OFF transient. The peak voltage of this transient decreased significantly with both increases in temperature and thermal overstress degradation. Figure 2 displays the switching transient voltage, measured near 330°C, at different degradation stages.

 

Figure 3: A scatter plot of the package temperature vs. switching transient peak voltage for a single IGBT under degradation.
Figure 3 shows a scatter plot of transient peak voltage versus heatsink temperature with grayscale indicating aging state. A degradation trend can be clearly seen with transient peaks in similar temperature ranges decreasing over 10% during the course of the experiment. An indicator of semiconductor degradation under severe conditions is clearly observed. The root-cause is of course in question. This indicator could be intrinsic degradation; however, a more likely cause is thermal impedance degradation of the package causing increases in internal temperatures. Further investigation of this failure precursor’s cause is planned.

Introduction

Post mortem analysis is a process that identifies the failure modes involved with electronic component failure through mechanical, electrical and chemical tools. Systematic identification is useful in determining the underlying physical failure mechanisms, which can ultimately lead to pinpointing the failure's root cause.

Techniques

The techniques involved with post mortem analysis span a broad application of tools and processes which can typically be accomplished within two failure analysis categories: non-destructive and destructive.
Non-Destructive Techniques
The non-destructive post-mortem technique involves non-altering means for analyzing the sample. No part of the sample undergoes chemical, electrical or mechanical related stress. Typically, non-destructive techniques involve quick external visual inspections, which can range from sophisticated microscopy methods to x-ray radiography analyses. Examples of non-destructive methods include the following:

External Visual Inspections

Electrical Characterizations

Optical Microscopy

X-ray Radiography

Curve Tracing

Destructive Techniques
Destructive techniques cause permanent and usually irreversible changes to the sample. This can be done by electrical, chemical or mechanical means, or a combination thereof. Typically, destructive techniques should proceed after non-destructive methods have been exhausted, because the outcome of this test is intended to cause physical alteration to the sample. The various applications of destructive failure analysis methods include:

Sectioning

Decapsulation

Scanning Electron Microscope (SEM)

Chemical Analysis

Heat Spot Detection

CASE STUDY - Insulated Gate Bipolar Transistor (IGBTS)

IGBT electronic components are important to investigate since they are quickly becoming the device of choice in electronic power engineering. Their hybrid structure, consisting of a BJT and MOSFET, makes them an attractive choice for designs which call for fast switching speed with minimal power consumption. Unfortunately, these components are not without their faults, and investigating these faults involves a broad range of tools and applications. Two non-destructive methods are explored below.
BACKGROUND
Several IGBTs that had undergone stress tests were examined. Based on the responses during tests, the parts were considered to have experienced only mild to medium damage. Electrical parameters of the two parts were measured and compared with the datasheet limits. Then, the parts were examined via X-Ray inspection using facilities in collaboration with CALCE (UMD).
X-RAY INSPECTION
The X-ray inspection revealed damage that may have occurred at the die-attach of the parts. The X-ray image of an un-stressed part is shown for comparison. The die attach at the stressed part shows possible voids. Such voids are likely to increase die temperature of the parts.



Figure 1: X-Rays of multistate degradation in IGBTs; a) unstressed component; b) component with mild operational damage; c) component with severe operational damage

Overview

The Discovery and Systems Health (DaSH) technical area focuses on understanding, modeling, and reasoning with engineering systems and science data. The work is centered around the emerging systems engineering discipline of Integrated Systems Health Management (ISHM). Under that umbrella, DaSH explores advances in machine learning, physics modeling, diagnostic and prognostic reasoning, and optimal decision making. DaSH is NASA’s premier ISHM research and development facility, with strengths in design of health management systems, ISHM systems engineering, sensor selection and optimization, monitoring, data analysis, fundamental physics investigations, prognostics, diagnostics, failure recovery, autonomous decision making, and uncertainty management.
DaSH is involved in engineering and analysis for a variety of NASA missions including aviation safety and security, science missions, human exploration, and the NASA Engineering Safety Center. In addition, DaSH also evaluates various quantum computing approaches where initial work has a focus on theoretical and empirical analysis of quantum annealing approaches to challenging optimization problems such as those posed by diagnostics and decision-making problems.
Some of the research areas of DaSH include:

• Analysis of complex physical phenomena
• Mathematical models representing physical systems
• Novel algorithms for health management
• Analysis of large data sets in aeronautics, earth science and cosmology
• Quantum computing
• Experimentally exploring failure phenomena (data released on public repositories)
• Improved engineering and scientific processes
• Integrated software products for flight and ground mission support

DaSH initiatives are supported by powerful research facilities, including a Quantum Computer and the SHARP Laboratory, which houses custom aging facilities for mechanical, electro-chemical, and electronic devices and hardware-in-the-loop experiments for algorithm benchmarking.

Technical Research Areas

Autonomous Systems and Robotics
Development of technologies required for systems that can adapt their behavior to complex, rapidly changing environments





Discovery and Systems Health
Tools and methods for systems health management; large-scale science and aeronautical data analysis and data mining


Robust Software Engineering
Increased software quality, reliability, and productivity through research done in the context of NASA applications